[Intel-gfx] [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes

[Maarten Lankhorst]

Op 16-08-18 om 14:55 schreef Juha-Pekka Heikkila:
> Enabling of P010, P012 and P016 formats. These formats will
> extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++++++++++-
>  drivers/gpu/drm/i915/intel_sprite.c  | 39 +++++++++++++++++++++++++++++++++++-
>  2 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 80ce742..5c7dc96 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
>  	DRM_FORMAT_NV12,
>  };
>  
> +static const uint32_t glk_primary_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_P010,
> +	DRM_FORMAT_P012,
> +	DRM_FORMAT_P016,
> +};
> +
>  static const uint64_t skl_format_modifiers_noccs[] = {
>  	I915_FORMAT_MOD_Yf_TILED,
>  	I915_FORMAT_MOD_Y_TILED,
> @@ -13721,7 +13740,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  		primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
>  						     PLANE_PRIMARY);
>  
> -		if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> +		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> +			intel_primary_formats = glk_primary_formats;
> +			num_formats = ARRAY_SIZE(glk_primary_formats);
> +		} else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
>  			intel_primary_formats = skl_pri_planar_formats;
>  			num_formats = ARRAY_SIZE(skl_pri_planar_formats);
>  		} else {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 68db026..5cc97ba 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1292,6 +1292,22 @@ static uint32_t skl_planar_formats[] = {
>  	DRM_FORMAT_NV12,
>  };
>  
> +static uint32_t glk_planar_formats[] = {
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_P010,
> +	DRM_FORMAT_P012,
> +	DRM_FORMAT_P016,
> +};
> +
>  static const uint64_t skl_plane_format_modifiers_noccs[] = {
>  	I915_FORMAT_MOD_Yf_TILED,
>  	I915_FORMAT_MOD_Y_TILED,
> @@ -1537,7 +1553,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>  	}
>  	intel_plane->base.state = &state->base;
>  
> -	if (INTEL_GEN(dev_priv) >= 9) {
> +	if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> +		intel_plane->can_scale = true;
> +		state->scaler_id = -1;
> +
> +		intel_plane->update_plane = skl_update_plane;
> +		intel_plane->disable_plane = skl_disable_plane;
> +		intel_plane->get_hw_state = skl_plane_get_hw_state;
> +
> +		if (skl_plane_has_planar(dev_priv, pipe,
> +					 PLANE_SPRITE0 + plane)) {
> +			plane_formats = glk_planar_formats;
> +			num_plane_formats = ARRAY_SIZE(glk_planar_formats);
> +		} else {
> +			plane_formats = skl_plane_formats;
> +			num_plane_formats = ARRAY_SIZE(skl_plane_formats);
> +		}
> +
> +		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
> +			modifiers = skl_plane_format_modifiers_ccs;
> +		else
> +			modifiers = skl_plane_format_modifiers_noccs;
> +	} else if (INTEL_GEN(dev_priv) >= 9) {
>  		intel_plane->can_scale = true;
>  		state->scaler_id = -1;
>  

Tested, still works ok against IGT. :)