[Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

[Tvrtko Ursulin]

On 22/08/18 15:29, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> According to the documentation, when programming the subslice count power-
> gating configuration register, the value to be written into it on Gen9LP
> should actually in the format of:
> 
>    1 slice  = 0x001
>    2 slices = 0x010
>    3 slices = 0x100
> 
> And not the popcount of the enabled subslice mask as on other platforms.
> 
> So on Gen9LP platforms we have been programming 0x11 into those bits, but
> the documentation does not explain what would that achieve. Could it be
> that we enable only two subslice on three sub-slice parts? Or hardware
> simply ignores it and sticks with the maximum configuration?
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Bspec: 12247

If it does turn out to be broken and this the correct fix then:

Fixes: 0cea6502bf9c ("drm/i915: Request full SSEU enablement on Gen9")

?

At that time code looked like:

+       if (INTEL_INFO(dev)->has_subslice_pg) {
+               rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
+               rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
+                       GEN8_RPCS_SS_CNT_SHIFT;
+               rpcs |= GEN8_RPCS_ENABLE;
+       }

So would had already most likely been broken.

Tvrtko


> ---
> Could this actually be true or I am severely misreading the docs? It does
> not sound plausible to me this would have been missed all this time..
> 
> How to test in what configuration do these parts run before and after this
> patch?
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 10 ++++++++--
>   1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 36050f085071..cdfa962a1975 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2508,9 +2508,15 @@ make_rpcs(struct drm_i915_private *dev_priv)
>   	}
>   
>   	if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
> +		u8 val;
> +
> +		val = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);
> +
> +		if (IS_GEN9_LP(dev_priv))
> +			val = BIT(val - 1);
> +
>   		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> -		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
> -			GEN8_RPCS_SS_CNT_SHIFT;
> +		rpcs |= val << GEN8_RPCS_SS_CNT_SHIFT;
>   		rpcs |= GEN8_RPCS_ENABLE;
>   	}
>   
>