[Intel-gfx] [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine

[Rodrigo Vivi]

On Thu, Aug 23, 2018 at 06:48:07PM -0700, Manasi Navare wrote:
> This patch fixes the PPS4 and PPS register definition macros that were
> resulting into an incorect MMIO address.
> 
> Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

(also checked others around to see if there was similar issues,
but the rest seems right)

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 41ab5b56ee52..64d7e675f7e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10488,7 +10488,7 @@ enum skl_power_gate {
>  							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
>  							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
>  #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
> -							   _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> +							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
>  							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
>  #define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
>  #define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
> @@ -10503,7 +10503,7 @@ enum skl_power_gate {
>  							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
>  							   _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
>  #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
> -							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> +							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
>  							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
>  #define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
>  #define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
> -- 
> 2.18.0
> 
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