[Intel-gfx] [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params
Manasi Navare
manasi.d.navare at intel.com
Tue Aug 28 22:47:21 UTC 2018
On Tue, Aug 28, 2018 at 03:18:56PM -0700, Srivatsa, Anusha wrote:
>
>
> >-----Original Message-----
> >From: Navare, Manasi D
> >Sent: Tuesday, July 31, 2018 2:07 PM
> >To: intel-gfx at lists.freedesktop.org
> >Cc: Singh, Gaurav K <gaurav.k.singh at intel.com>; Jani Nikula
> ><jani.nikula at linux.intel.com>; Ville Syrjala <ville.syrjala at linux.intel.com>;
> >Srivatsa, Anusha <anusha.srivatsa at intel.com>; Navare, Manasi D
> ><manasi.d.navare at intel.com>
> >Subject: [PATCH v2 15/23] drm/i915/dsc: Define & Compute VESA DSC params
> >
> >From: Gaurav K Singh <gaurav.k.singh at intel.com>
> >
> >This patches does the following:
> >
> >1. This patch defines all the DSC parameters as per the VESA DSC specification.
> >These are stored in the encoder and used to compute the PPS parameters to be
> >sent to the Sink.
> >2. Compute all the DSC parameters which are derived from DSC state of
> >intel_crtc_state.
> >3. Compute all parameters that are VESA DSC specific
> >
> >This computation happens in the atomic check phase during
> >compute_config() to validate if display stream compression can be enabled for
> >the requested mode.
> >
> >v5 (From Manasi):
> >* Add logic to limit the max line buf depth for DSC 1.1 to 13 as per DSC 1.1 spec
> >* Fix dim checkpatch warnings/checks
> >
> >v4 (From Gaurav):
> >* Rebase on latest drm tip
> >* rename variable name(Manasi)
> >* Populate linebuf_depth variable(Manasi)
> >
> >v3 (From Gaurav):
> >* Rebase my previous patches on top of Manasi's latest patch series
> >* Using >>n rather than /2^n (Manasi)
> >* Change the commit message to explain what the patch is doing(Gaurav)
> >
> >Fixed review comments from Ville:
> >* Don't use macro TWOS_COMPLEMENT
> >* Mention in comment about the source of RC params
> >* Return directly from case statements
> >* Using single asssignment for assigning rc_range_params
> >* Using <<n rather than *2^n and removing the comments about the fixed point
> >numbers
> >
> >v2 (From Manasi):
> >* Update logic for minor version to consider the dpcd value and what supported
> >by the HW platform
> >* Use DRM DSC config struct instead of intel_dp struct
> >* Move the DSC constants to DRM DSC header file
> >* Use u16, u8 where bigger data types not needed
> >* * Compute the DSC parameters as part of DSC compute config since the
> >computation can fail (Manasi)
> >
> >Cc: Jani Nikula <jani.nikula at linux.intel.com>
> >Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
> >Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> >Cc: Gaurav K Singh <gaurav.k.singh at intel.com>
> >Signed-off-by: Gaurav K Singh <gaurav.k.singh at intel.com>
> >Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
> >---
> > drivers/gpu/drm/i915/Makefile | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 7 +
> > drivers/gpu/drm/i915/intel_drv.h | 4 +
> > drivers/gpu/drm/i915/intel_vdsc.c | 455
> >++++++++++++++++++++++++++++++++++++++
> > include/drm/drm_dp_helper.h | 3 +
> > include/drm/drm_dsc.h | 2 +-
> > 6 files changed, 472 insertions(+), 2 deletions(-) create mode 100644
> >drivers/gpu/drm/i915/intel_vdsc.c
> >
> >diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> >index 5794f10..deaf2d4 100644
> >--- a/drivers/gpu/drm/i915/Makefile
> >+++ b/drivers/gpu/drm/i915/Makefile
> >@@ -153,7 +153,8 @@ i915-y += dvo_ch7017.o \
> > intel_sdvo.o \
> > intel_tv.o \
> > vlv_dsi.o \
> >- vlv_dsi_pll.o
> >+ vlv_dsi_pll.o \
> >+ intel_vdsc.o
> >
> > # Post-mortem debug and GPU hang state capture
> > i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o diff --git
> >a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index
> >7132f52..dc0a3c2 100644
> >--- a/drivers/gpu/drm/i915/intel_dp.c
> >+++ b/drivers/gpu/drm/i915/intel_dp.c
> >@@ -2042,6 +2042,13 @@ static bool intel_dp_dsc_compute_config(struct
> >intel_dp *intel_dp,
> > return false;
> > }
> > }
> >+ if (intel_dp_compute_dsc_params(intel_dp, pipe_config) < 0) {
> >+ DRM_ERROR("Cannot compute valid DSC parameters for Input
> >Bpp = %d"
> >+ "Compressed BPP = %d\n",
> >+ pipe_config->pipe_bpp,
> >+ pipe_config->dsc_params.compressed_bpp);
> >+ return false;
> >+ }
> > pipe_config->dsc_params.compression_enable = true;
> > DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
> > "Compressed Bpp = %d Slice Count = %d\n", diff --git
> >a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >index b7c2652..33cc777 100644
> >--- a/drivers/gpu/drm/i915/intel_drv.h
> >+++ b/drivers/gpu/drm/i915/intel_drv.h
> >@@ -1749,6 +1749,10 @@ uint16_t intel_dp_dsc_get_output_bpp(int link_clock,
> >uint8_t lane_count, uint8_t intel_dp_dsc_get_slice_count(struct intel_dp
> >*intel_dp, int mode_clock,
> > int mode_hdisplay);
> >
> >+/* intel_vdsc.c */
> >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> >+ struct intel_crtc_state *pipe_config);
> >+
> > static inline unsigned int intel_dp_unused_lane_mask(int lane_count) {
> > return ~((1 << lane_count) - 1) & 0xf; diff --git
> >a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
> >new file mode 100644
> >index 0000000..ecd270c
> >--- /dev/null
> >+++ b/drivers/gpu/drm/i915/intel_vdsc.c
> >@@ -0,0 +1,455 @@
> >+/*
> >+ * Copyright © 2018 Intel Corporation
> >+ *
> >+ * Permission is hereby granted, free of charge, to any person
> >+obtaining a
> >+ * copy of this software and associated documentation files (the
> >+"Software"),
> >+ * to deal in the Software without restriction, including without
> >+limitation
> >+ * the rights to use, copy, modify, merge, publish, distribute,
> >+sublicense,
> >+ * and/or sell copies of the Software, and to permit persons to whom
> >+the
> >+ * Software is furnished to do so, subject to the following conditions:
> >+ *
> >+ * The above copyright notice and this permission notice (including the
> >+next
> >+ * paragraph) shall be included in all copies or substantial portions
> >+of the
> >+ * Software.
> >+ *
> >+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >+EXPRESS OR
> >+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >+MERCHANTABILITY,
> >+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> >EVENT
> >+SHALL
> >+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> >DAMAGES OR
> >+OTHER
> >+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >+ARISING
> >+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> >OTHER
> >+ * DEALINGS IN THE SOFTWARE.
> >+ *
> >+ * Author: Gaurav K Singh <gaurav.k.singh at intel.com>
> >+ * Manasi Navare <manasi.d.navare at intel.com>
> >+ */
> >+
> >+#include <drm/drmP.h>
> >+#include <drm/i915_drm.h>
> >+#include "i915_drv.h"
> >+#include "intel_drv.h"
> >+
> >+enum ROW_INDEX_BPP {
> >+ ROW_INDEX_6BPP = 0,
> >+ ROW_INDEX_8BPP,
> >+ ROW_INDEX_10BPP,
> >+ ROW_INDEX_12BPP,
> >+ ROW_INDEX_15BPP,
> >+ MAX_ROW_INDEX
> >+};
> >+
> >+enum COLUMN_INDEX_BPC {
> >+ COLUMN_INDEX_8BPC = 0,
> >+ COLUMN_INDEX_10BPC,
> >+ COLUMN_INDEX_12BPC,
> >+ COLUMN_INDEX_14BPC,
> >+ COLUMN_INDEX_16BPC,
> >+ MAX_COLUMN_INDEX
> >+};
> >+
> >+#define DSC_SUPPORTED_VERSION_MIN 1
> >+
> >+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically
> >+constant */ static u16 rc_buf_thresh[] = {
> >+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
> >+ 7744, 7872, 8000, 8064
> >+};
> >+
> >+struct rc_parameters {
> >+ u16 initial_xmit_delay;
> >+ u8 first_line_bpg_offset;
> >+ u16 initial_offset;
> >+ u8 flatness_min_qp;
> >+ u8 flatness_max_qp;
> >+ u8 rc_quant_incr_limit0;
> >+ u8 rc_quant_incr_limit1;
> >+ struct dsc_rc_range_parameters
> >rc_range_params[DSC_NUM_BUF_RANGES];
> >+};
> >+
> >+/*
> >+ * Selected Rate Control Related Parameter Recommended Values
> >+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212 */ static
> >+struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = { {
> >+ /* 6BPP/8BPC */
> >+ { 768, 15, 6144, 3, 13, 11, 11, {
> >+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> >+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> >+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> >+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> >+ }
> >+ },
> >+ /* 6BPP/10BPC */
> >+ { 768, 15, 6144, 7, 17, 15, 15, {
> >+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> >+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> >+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> >+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> >+ { 17, 18, -12 }
> >+ }
> >+ },
> >+ /* 6BPP/12BPC */
> >+ { 768, 15, 6144, 11, 21, 19, 19, {
> >+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> >+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> >+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> >+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> >+ { 21, 22, -12 }
> >+ }
> >+ },
> >+ /* 6BPP/14BPC */
> >+ { 768, 15, 6144, 15, 25, 23, 27, {
> >+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> >+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> >+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> >+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> >+ { 25, 26, -12 }
> >+ }
> >+ },
> >+ /* 6BPP/16BPC */
> >+ { 768, 15, 6144, 19, 29, 27, 27, {
> >+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> >+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> >+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> >+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> >+ { 29, 30, -12 }
> >+ }
> >+ },
> >+},
> >+{
> >+ /* 8BPP/8BPC */
> >+ { 512, 12, 6144, 3, 12, 11, 11, {
> >+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >+ }
> >+ },
> >+ /* 8BPP/10BPC */
> >+ { 512, 12, 6144, 7, 16, 15, 15, {
> >+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >+ }
> >+ },
> >+ /* 8BPP/12BPC */
> >+ { 512, 12, 6144, 11, 20, 19, 19, {
> >+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >+ { 21, 23, -12 }
> >+ }
> >+ },
> >+ /* 8BPP/14BPC */
> >+ { 512, 12, 6144, 15, 24, 23, 23, {
> >+ { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> >+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> >+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> >+ { 24, 25, -12 }
> >+ }
> >+ },
> >+ /* 8BPP/16BPC */
> >+ { 512, 12, 6144, 19, 28, 27, 27, {
> >+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> >+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> >+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> >+ { 28, 29, -12 }
> >+ }
> >+ },
> >+},
> >+{
> >+ /* 10BPP/8BPC */
> >+ { 410, 15, 5632, 3, 12, 11, 11, {
> >+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> >+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> >+ }
> >+ },
> >+ /* 10BPP/10BPC */
> >+ { 410, 15, 5632, 7, 16, 15, 15, {
> >+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> >+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> >+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> >+ }
> >+ },
> >+ /* 10BPP/12BPC */
> >+ { 410, 15, 5632, 11, 20, 19, 19, {
> >+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> >+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> >+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> >+ { 19, 20, -12 }
> >+ }
> >+ },
> >+ /* 10BPP/14BPC */
> >+ { 410, 15, 5632, 15, 24, 23, 23, {
> >+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> >+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> >+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> >+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> >+ { 23, 24, -12 }
> >+ }
> >+ },
> >+ /* 10BPP/16BPC */
> >+ { 410, 15, 5632, 19, 28, 27, 27, {
> >+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> >+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> >+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> >+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> >+ { 27, 28, -12 }
> >+ }
> >+ },
> >+},
> >+{
> >+ /* 12BPP/8BPC */
> >+ { 341, 15, 2048, 3, 12, 11, 11, {
> >+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >+ }
> >+ },
> >+ /* 12BPP/10BPC */
> >+ { 341, 15, 2048, 7, 16, 15, 15, {
> >+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >+ }
> >+ },
> >+ /* 12BPP/12BPC */
> >+ { 341, 15, 2048, 11, 20, 19, 19, {
> >+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >+ { 21, 23, -12 }
> >+ }
> >+ },
> >+ /* 12BPP/14BPC */
> >+ { 341, 15, 2048, 15, 24, 23, 23, {
> >+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> >+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> >+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> >+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> >+ { 22, 23, -12 }
> >+ }
> >+ },
> >+ /* 12BPP/16BPC */
> >+ { 341, 15, 2048, 19, 28, 27, 27, {
> >+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> >+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> >+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> >+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> >+ { 26, 27, -12 }
> >+ }
> >+ },
> >+},
> >+{
> >+ /* 15BPP/8BPC */
> >+ { 273, 15, 2048, 3, 12, 11, 11, {
> >+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> >+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> >+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> >+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> >+ }
> >+ },
> >+ /* 15BPP/10BPC */
> >+ { 273, 15, 2048, 7, 16, 15, 15, {
> >+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> >+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> >+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> >+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> >+ }
> >+ },
> >+ /* 15BPP/12BPC */
> >+ { 273, 15, 2048, 11, 20, 19, 19, {
> >+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> >+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> >+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> >+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> >+ { 16, 17, -12 }
> >+ }
> >+ },
> >+ /* 15BPP/14BPC */
> >+ { 273, 15, 2048, 15, 24, 23, 23, {
> >+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> >+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> >+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> >+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> >+ { 20, 21, -12 }
> >+ }
> >+ },
> >+ /* 15BPP/16BPC */
> >+ { 273, 15, 2048, 19, 28, 27, 27, {
> >+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> >+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> >+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> >+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> >+ { 24, 25, -12 }
> >+ }
> >+ }
> >+}
> >+};
> >+
> >+static int get_row_index_for_rc_params(u16 compressed_bpp) {
> >+ switch (compressed_bpp) {
> >+ case 6:
> >+ return ROW_INDEX_6BPP;
> >+ case 8:
> >+ return ROW_INDEX_8BPP;
> >+ case 10:
> >+ return ROW_INDEX_10BPP;
> >+ case 12:
> >+ return ROW_INDEX_12BPP;
> >+ case 15:
> >+ return ROW_INDEX_15BPP;
> >+ default:
> >+ return -EINVAL;
> >+ }
> >+}
> >+
> >+static int get_column_index_for_rc_params(u8 bits_per_component) {
> >+ switch (bits_per_component) {
> >+ case 8:
> >+ return COLUMN_INDEX_8BPC;
> >+ case 10:
> >+ return COLUMN_INDEX_10BPC;
> >+ case 12:
> >+ return COLUMN_INDEX_12BPC;
> >+ case 14:
> >+ return COLUMN_INDEX_14BPC;
> >+ case 16:
> >+ return COLUMN_INDEX_16BPC;
> >+ default:
> >+ return -EINVAL;
> >+ }
> >+}
> >+
> >+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
> >+ struct intel_crtc_state *pipe_config) {
> >+ struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
> >+ u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
> >+ u8 i = 0;
> >+ u8 row_index = 0;
> >+ u8 column_index = 0;
> >+ u8 line_buf_depth = 0;
> >+
> >+ vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
> >+ vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
> >+ vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> >+ pipe_config-
> >>dsc_params.slice_count);
> >+ /*
> >+ * Slice Height of 8 works for all currently available panels. So start
> >+ * with that if pic_height is an integral multiple of 8.
> >+ * Eventually add logic to try multiple slice heights.
> >+ */
> >+ if (vdsc_cfg->pic_height % 8 == 0)
> >+ vdsc_cfg->slice_height = 8;
> >+ else if (vdsc_cfg->pic_height % 4 == 0)
> >+ vdsc_cfg->slice_height = 4;
> >+ else
> >+ vdsc_cfg->slice_height = 2;
> >+
> >+ /* Values filled from DSC Sink DPCD */
> >+ vdsc_cfg->dsc_version_major = (intel_dp->dsc_dpcd[DP_DSC_REV -
> >DP_DSC_SUPPORT] &
> >+ DP_DSC_MAJOR_MASK) >>
> >DP_DSC_MAJOR_SHIFT;
> >+ vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN,
> >+ (intel_dp->dsc_dpcd[DP_DSC_REV -
> >DP_DSC_SUPPORT] &
> >+ DP_DSC_MINOR_MASK) >>
> >DP_DSC_MINOR_SHIFT);
> >+
> >+ vdsc_cfg->convert_rgb = intel_dp-
> >>dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> >+ DP_DSC_RGB;
> >+
> >+ line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
> >+ if (vdsc_cfg->dsc_version_minor == 2)
> >+ vdsc_cfg->line_buf_depth = (line_buf_depth ==
> >DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
> >+ DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
> Shouldn't this be line_buf_depth >= DSC_1_2_MAX_LINEBUF_DEPTH_BITS?
If you look at drm_dp_dsc_sink_line_buf_depth() function, it will only return maximum of 16.
Greater than DSC_1_2_MAX_LINEBUF_DEPTH_BITS is not a valid value and the function will return 0 for that.
>
> >+ else
> >+ vdsc_cfg->line_buf_depth = (line_buf_depth >
> Line_buf_depth >= DSC_1_1_MAX_LINEBUF_DEPTH_BITS??
This should be only greater than since if its equal to the max then it can just use the maximum value.
Manasi
>
> Anusha
> >DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
> >+ DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
> >+
> >+ /* Gen 11 does not support YCbCr */
> >+ vdsc_cfg->enable422 = false;
> >+ /* Gen 11 does not support VBR */
> >+ vdsc_cfg->vbr_enable = false;
> >+ vdsc_cfg->block_pred_enable =
> >+ intel_dp-
> >>dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
> >+ DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
> >+
> >+ /* Gen 11 only supports integral values of bpp */
> >+ vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> >+ vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> >+
> >+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
> >+ /*
> >+ * six 0s are appended to the lsb of each threshold value
> >+ * internally in h/w.
> >+ * Only 8 bits are allowed for programming RcBufThreshold
> >+ */
> >+ vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
> >+ }
> >+
> >+ /*
> >+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
> >+ * as per C Model
> >+ */
> >+ if (compressed_bpp == 6) {
> >+ vdsc_cfg->rc_buf_thresh[12] = 0x7C;
> >+ vdsc_cfg->rc_buf_thresh[13] = 0x7D;
> >+ }
> >+
> >+ row_index = get_row_index_for_rc_params(compressed_bpp);
> >+ column_index =
> >+ get_column_index_for_rc_params(vdsc_cfg-
> >>bits_per_component);
> >+
> >+ if (row_index < 0 || column_index < 0)
> >+ return -EINVAL;
> >+
> >+ vdsc_cfg->first_line_bpg_offset =
> >+ rc_params[row_index][column_index].first_line_bpg_offset;
> >+ vdsc_cfg->initial_xmit_delay =
> >+ rc_params[row_index][column_index].initial_xmit_delay;
> >+ vdsc_cfg->initial_offset =
> >+ rc_params[row_index][column_index].initial_offset;
> >+ vdsc_cfg->flatness_min_qp =
> >+ rc_params[row_index][column_index].flatness_min_qp;
> >+ vdsc_cfg->flatness_max_qp =
> >+ rc_params[row_index][column_index].flatness_max_qp;
> >+ vdsc_cfg->rc_quant_incr_limit0 =
> >+ rc_params[row_index][column_index].rc_quant_incr_limit0;
> >+ vdsc_cfg->rc_quant_incr_limit1 =
> >+ rc_params[row_index][column_index].rc_quant_incr_limit1;
> >+
> >+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++)
> >+ vdsc_cfg->rc_range_params[i] =
> >+
> > rc_params[row_index][column_index].rc_range_params[i];
> >+
> >+ /*
> >+ * BitsPerComponent value determines mux_word_size:
> >+ * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64
> >bits
> >+ * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
> >+ * 48 bits
> >+ */
> >+ if (vdsc_cfg->bits_per_component == 8 ||
> >+ vdsc_cfg->bits_per_component == 10)
> >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> >+ else if (vdsc_cfg->bits_per_component == 12)
> >+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
> >+
> >+ /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
> >+ vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
> >+ (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
> >+
> >+ return 0;
> >+}
> >diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
> >0cf2407..f178933 100644
> >--- a/include/drm/drm_dp_helper.h
> >+++ b/include/drm/drm_dp_helper.h
> >@@ -186,6 +186,9 @@
> >
> > #define DP_GUID 0x030 /* 1.2 */
> >
> >+#define DP_DSC_RC_PIXELS_PER_GROUP 3
> >+#define DP_DSC_SCALE_DECREMENT_INTERVAL_MAX 4095
> >+
> > #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
> > # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
> >
> >diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index
> >4cfcd03..796c798 100644
> >--- a/include/drm/drm_dsc.h
> >+++ b/include/drm/drm_dsc.h
> >@@ -67,7 +67,7 @@ struct dsc_rc_range_parameters {
> > /* Max Quantization Parameters allowed for this range */
> > u8 range_max_qp;
> > /* Bits/group offset to apply to target for this group */
> >- u8 range_bpg_offset;
> >+ s8 range_bpg_offset;
> > };
> >
> > struct drm_dsc_config {
> >--
> >2.7.4
>
More information about the Intel-gfx
mailing list