[Intel-gfx] [PATCH v2 06/11] drm: Add the PSR SU granularity registers offsets

[Dhinakaran Pandiyan]

On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> Source is required to comply to sink SU granularity when
> DP_PSR2_SU_GRANULARITY_REQUIRED is set in DP_PSR_CAPS,
> so adding the registers offsets.
> 
> v2: Also adding DP_PSR2_SU_Y_GRANULARITY(Rodrigo)
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  include/drm/drm_dp_helper.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h
> b/include/drm/drm_dp_helper.h
> index 047314ce25d6..0e04b2db3dde 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -314,6 +314,10 @@
>  # define DP_PSR_SETUP_TIME_SHIFT            1
>  # define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
>  # define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
> +
> +#define DP_PSR2_SU_X_GRANULARITY	    0x072 /* eDP 1.4b */
> +#define DP_PSR2_SU_Y_GRANULARITY	    0x074 /* eDP 1.4b */
Definitions above use spaces instead of tabs, so it'd have been good to
be consistent. But, there are places in the file where tabs are used
too, so will leave it to you if you want to switch.

> +
Verified against eDP spec 1.4b
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>

>  /*
>   * 0x80-0x8f describe downstream port capabilities, but there are
> two layouts
>   * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it
> was not,