[Intel-gfx] [PATCH 3/8] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

Mika Kuoppala mika.kuoppala at linux.intel.com
Mon Dec 3 12:05:25 UTC 2018


Chris Wilson <chris at chris-wilson.co.uk> writes:

> Ensure that the sync registers are cleared every time we restart the
> ring to avoid stale values from creeping in from random neutrinos.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 992889f9e0ff..81b10d85b738 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -529,6 +529,13 @@ static int init_ring_common(struct intel_engine_cs *engine)
>  
>  	intel_engine_reset_breadcrumbs(engine);
>  
> +	if (HAS_LEGACY_SEMAPHORES(engine->i915)) {
> +		I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
> +		I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
> +		if (HAS_VEBOX(dev_priv))

Minor nitpick: mixed i915 and dev_priv usage. 

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> +			I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
> +	}
> +
>  	/* Enforce ordering by reading HEAD register back */
>  	I915_READ_HEAD(engine);
>  
> -- 
> 2.20.0.rc1


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