[Intel-gfx] [PATCH v3 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE
Jani Nikula
jani.nikula at linux.intel.com
Tue Dec 11 14:24:57 UTC 2018
On Wed, 05 Dec 2018, Lucas De Marchi <lucas.demarchi at intel.com> wrote:
> RANGE makes it longer, but clearer. We are also going to add a macro to
> check an individual gen, so add the _RANGE prefix here.
>
> Diff generated with:
>
> sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/{*/,}*.{c,h} -i
>
> v2: use IS_GEN rather than GT_GEN
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
For this one patch,
Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 4 ++--
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++----
> drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
> 8 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0689e67c966e..affcb028ff8d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2213,7 +2213,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> GENMASK((e) - 1, (s) - 1))
>
> /* Returns true if Gen is in inclusive range [Start, End] */
> -#define IS_GEN(dev_priv, s, e) \
> +#define IS_GEN_RANGE(dev_priv, s, e) \
> (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 4529edfdcfc8..ad0095be435d 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1796,7 +1796,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
> * be read back from automatically triggered reports, as part of the
> * RPT_ID field.
> */
> - if (IS_GEN(dev_priv, 9, 11)) {
> + if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> I915_WRITE(GEN8_OA_DEBUG,
> _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
> GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
> @@ -3442,7 +3442,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>
> dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
> }
> - } else if (IS_GEN(dev_priv, 10, 11)) {
> + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
> dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> gen7_is_valid_b_counter_addr;
> dev_priv->perf.oa.ops.is_valid_mux_reg =
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 6d3e0260d49c..7b7e7abfa259 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -453,7 +453,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
> * Only parse SDVO mappings on gens that could have SDVO. This isn't
> * accurate and doesn't have to be, as long as it's not too strict.
> */
> - if (!IS_GEN(dev_priv, 3, 7)) {
> + if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
> DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index af2873403009..fe5e87b6e1af 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1248,7 +1248,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
> &engine->execlists;
> u64 addr;
>
> - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
> + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
> drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
> drm_printf(m, "\tRING_START: 0x%08x\n",
> I915_READ(RING_START(engine->mmio_base)));
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 78dbacdeaece..b57e31fc0f1e 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -787,7 +787,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> * having a Y offset that isn't divisible by 4 causes FIFO underrun
> * and screen flicker.
> */
> - if (IS_GEN(dev_priv, 9, 10) &&
> + if (IS_GEN_RANGE(dev_priv, 9, 10) &&
> (fbc->state_cache.plane.adjusted_y & 3)) {
> fbc->no_fbc_reason = "plane Y offset is misaligned";
> return false;
> diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c
> index e26d05a46451..41921a843d42 100644
> --- a/drivers/gpu/drm/i915/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/intel_hangcheck.c
> @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
> return ENGINE_WAIT_KICK;
> }
>
> - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
> + if (IS_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) {
> switch (semaphore_passed(engine)) {
> default:
> return ENGINE_DEAD;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c5eb26a7ee79..a205cc9e60cc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -436,7 +436,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> POSTING_READ(mmio);
>
> /* Flush the TLB for this page */
> - if (IS_GEN(dev_priv, 6, 7)) {
> + if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> i915_reg_t reg = RING_INSTPM(engine->mmio_base);
>
> /* ring should be idle before issuing a sync flush*/
> @@ -670,7 +670,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> return ret;
>
> /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> - if (IS_GEN(dev_priv, 4, 6))
> + if (IS_GEN_RANGE(dev_priv, 4, 6))
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
>
> /* We need to disable the AsyncFlip performance optimisations in order
> @@ -679,7 +679,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> *
> * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> */
> - if (IS_GEN(dev_priv, 6, 7))
> + if (IS_GEN_RANGE(dev_priv, 6, 7))
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>
> /* Required for the hardware to program scanline values for waiting */
> @@ -704,7 +704,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
> _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> }
>
> - if (IS_GEN(dev_priv, 6, 7))
> + if (IS_GEN_RANGE(dev_priv, 6, 7))
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> if (INTEL_GEN(dev_priv) >= 6)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 9289515108c3..631b4165fe00 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> dev_priv->uncore.pmic_bus_access_nb.notifier_call =
> i915_pmic_bus_access_notifier;
>
> - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
> + if (IS_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) {
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2);
> } else if (IS_GEN5(dev_priv)) {
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5);
> - } else if (IS_GEN(dev_priv, 6, 7)) {
> + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6);
>
> if (IS_VALLEYVIEW(dev_priv)) {
> @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
> }
> - } else if (IS_GEN(dev_priv, 9, 10)) {
> + } else if (IS_GEN_RANGE(dev_priv, 9, 10)) {
> ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
> ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
> ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
> @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
> } else if (INTEL_GEN(dev_priv) >= 6) {
> fw_domains = __gen6_reg_read_fw_domains(offset);
> } else {
> - WARN_ON(!IS_GEN(dev_priv, 2, 5));
> + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> fw_domains = 0;
> }
>
> @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
> fw_domains = __fwtable_reg_write_fw_domains(offset);
> } else if (IS_GEN8(dev_priv)) {
> fw_domains = __gen8_reg_write_fw_domains(offset);
> - } else if (IS_GEN(dev_priv, 6, 7)) {
> + } else if (IS_GEN_RANGE(dev_priv, 6, 7)) {
> fw_domains = FORCEWAKE_RENDER;
> } else {
> - WARN_ON(!IS_GEN(dev_priv, 2, 5));
> + WARN_ON(!IS_GEN_RANGE(dev_priv, 2, 5));
> fw_domains = 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
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