[Intel-gfx] [PATCH] drm/i915: Apply missed interrupt after reset w/a to all ringbuffer gen

[Tvrtko Ursulin]

On 13/12/2018 08:53, Chris Wilson wrote:
> Having completed a test run of gem_eio across all machines in CI we also
> observe the phenomenon (of lost interrupts after resetting the GPU) on
> gen3 machines as well as the previously sighted gen6/gen7. Let's apply
> the same HWSTAM workaround that was effective for gen6+ for all, as
> although we haven't seen the same failure on gen4/5 it seems prudent to
> keep the code the same.
> 
> As a consequence we can remove the extra setting of HWSTAM and apply the
> register from a single site.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108735
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/i915_irq.c         |  9 ---------
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 16 ++++++++++++----
>   2 files changed, 12 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index e2dac9b5f4ce..0c7fc9890891 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3586,9 +3586,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(dev);
>   
> -	if (IS_GEN(dev_priv, 5))
> -		I915_WRITE(HWSTAM, 0xffffffff);
> -
>   	GEN3_IRQ_RESET(DE);
>   	if (IS_GEN(dev_priv, 7))
>   		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
> @@ -4368,8 +4365,6 @@ static void i8xx_irq_reset(struct drm_device *dev)
>   
>   	i9xx_pipestat_irq_reset(dev_priv);
>   
> -	I915_WRITE16(HWSTAM, 0xffff);
> -
>   	GEN2_IRQ_RESET();
>   }
>   
> @@ -4537,8 +4532,6 @@ static void i915_irq_reset(struct drm_device *dev)
>   
>   	i9xx_pipestat_irq_reset(dev_priv);
>   
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>   	GEN3_IRQ_RESET();
>   }
>   
> @@ -4648,8 +4641,6 @@ static void i965_irq_reset(struct drm_device *dev)
>   
>   	i9xx_pipestat_irq_reset(dev_priv);
>   
> -	I915_WRITE(HWSTAM, 0xffffffff);
> -
>   	GEN3_IRQ_RESET();
>   }
>   
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdeca2b877c9..07e47023f557 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -428,17 +428,25 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>   		mmio = RING_HWS_PGA(engine->mmio_base);
>   	}
>   
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +	if (1) {

A tad too lazy. :) Suggest a helper function some_appropriate_name(engine);

Regards,

Tvrtko

> +		i915_reg_t hwstam = RING_HWSTAM(engine->mmio_base);
>   		u32 mask = ~0u;
>   
>   		/*
>   		 * Keep the render interrupt unmasked as this papers over
>   		 * lost interrupts following a reset.
>   		 */
> -		if (engine->id == RCS)
> -			mask &= ~BIT(0);
> +		if (engine->id == RCS) {
> +			if (INTEL_GEN(dev_priv) >= 6)
> +				mask &= ~BIT(0);
> +			else
> +				mask &= ~I915_USER_INTERRUPT;
> +		}
>   
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
> +		if (INTEL_GEN(dev_priv) >= 3)
> +			I915_WRITE(hwstam, mask);
> +		else
> +			I915_WRITE16(hwstam, mask);
>   	}
>   
>   	I915_WRITE(mmio, engine->status_page.ggtt_offset);
>