[Intel-gfx] [PATCH 1/3] drm/i915: Prepare for larger CSB status FIFO size

[Chris Wilson]

Quoting Mika Kuoppala (2018-12-19 12:27:22)
> Make csb entry count variable in preparation for larger
> CSB status FIFO size found on gen11+ hardware.
> 
> v2: adapt to hwsp access only (Chris)
>     non continuous mmio (Daniele)
> v3: entries (Chris), fix macro for checkpatch
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> @@ -867,6 +867,7 @@ static void process_csb(struct intel_engine_cs *engine)
>         struct intel_engine_execlists * const execlists = &engine->execlists;
>         struct execlist_port *port = execlists->port;
>         const u32 * const buf = execlists->csb_status;
> +       const u8 entries = execlists->csb_size;
>         u8 head, tail;
>  
>         /*
> @@ -900,7 +901,7 @@ static void process_csb(struct intel_engine_cs *engine)
>                 unsigned int status;
>                 unsigned int count;
>  
> -               if (++head == GEN8_CSB_ENTRIES)
> +               if (++head == entries)

Fwiw, I would go with s/entries/num_entries/
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris