[Intel-gfx] [PATCH 3/6] drm/i915/ringbuffer: Remove irq-seqno w/a for gen6 xcs

[Tvrtko Ursulin]

On 28/12/2018 17:16, Chris Wilson wrote:
> The MI_FLUSH_DW does appear coherent with the following
> MI_USER_INTERRUPT, but only on Sandybridge. Ivybridge requires a heavier
> hammer, but on Sandybridge we can stop requiring the irq_seqno barrier.
> 
> Testcase: igt/gem_sync
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1b9264883a8d..2fb3a364c390 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2260,7 +2260,8 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
>   
>   		engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
>   		engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> -		engine->irq_seqno_barrier = gen6_seqno_barrier;
> +		if (!IS_GEN(dev_priv, 6))
> +			engine->irq_seqno_barrier = gen6_seqno_barrier;
>   	} else {
>   		engine->emit_flush = bsd_ring_flush;
>   		if (IS_GEN(dev_priv, 5))
> @@ -2285,7 +2286,8 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
>   
>   	engine->emit_breadcrumb = gen6_xcs_emit_breadcrumb;
>   	engine->emit_breadcrumb_sz = gen6_xcs_emit_breadcrumb_sz;
> -	engine->irq_seqno_barrier = gen6_seqno_barrier;
> +	if (!IS_GEN(dev_priv, 6))
> +		engine->irq_seqno_barrier = gen6_seqno_barrier;
>   
>   	return intel_init_ring_buffer(engine);
>   }
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Regards,

Tvrtko