[Intel-gfx] [PATCH 5/7] drm/i915: Expose RPCS (SSEU) configuration to userspace (Gen11 only)

Tvrtko Ursulin tvrtko.ursulin at linux.intel.com
Mon Dec 31 15:39:54 UTC 2018


On 31/12/2018 15:33, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-12-31 15:21:15)
>>
>> On 14/12/2018 13:33, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2018-12-14 12:34:47)
>>>> +static int get_sseu(struct i915_gem_context *ctx,
>>>> +                   struct drm_i915_gem_context_param *args)
>>>> +{
>>>> +       struct drm_i915_gem_context_param_sseu user_sseu;
>>>> +       struct intel_engine_cs *engine;
>>>> +       struct intel_context *ce;
>>>> +       int ret;
>>>> +
>>>> +       if (args->size == 0)
>>>> +               goto out;
>>>> +       else if (args->size < sizeof(user_sseu))
>>>> +               return -EINVAL;
>>>> +
>>>> +       if (copy_from_user(&user_sseu, u64_to_user_ptr(args->value),
>>>> +                          sizeof(user_sseu)))
>>>> +               return -EFAULT;
>>>> +
>>>> +       if (user_sseu.rsvd1 || user_sseu.rsvd2)
>>>> +               return -EINVAL;
>>>
>>> I'd vote for s/rsvd2/flags/ straight away as already I can suggest we
>>> allow for USE_CTX_ENGINE to swap class/instance for engine-id so that we
>>> can set rpcs for, and not least, a virtual engine.
>>
>> Hm.. would it be useful? It would just be a way of indirection.
>>
>> engines = [vcs:0, vcs:1]
>> ctx.set_map(engines)
>>
>> And then a):
>>
>> foreach engine in engines:
>>          ctx.set_sseu(engine, flags=0)
>>
>> vs b):
>>
>> for i = 0; i < len(engines); i++:
>>          ctx.set_sseu(i, flags=USE_CTX_ENGINE)
>>
>> So I don't see any benefit. But maybe I missed your idea.
> 
> The virtual engine doesn't have a valid class:instance, only its index
> in the per-context engines[]. And we want to control its context image,
> not the context images on each of the real engine.

True. At first I was thinking that it is equivalent to setting SSEU to 
all engines from the map but of course we only have one context image.. 
Okay, I will rename this to flags straight away.

Regards,

Tvrtko


More information about the Intel-gfx mailing list