[Intel-gfx] [PATCH v2] drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.

[Rodrigo Vivi]

On Fri, Jan 05, 2018 at 05:48:35PM +0000, Mark Janes wrote:
> Tested-by: Mark Janes <mark.a.janes at intel.com>

Thanks for that and sorry for missing it before merging :(
Also I don't know why patchwork didn't get it automatically.

> 
> Geminilake GPU hangs caused by tesselation tests in VulkanCTS and GLCTS
> are fixed by the Mesa patch that toggles this bit.
> 
> Kenneth Graunke <kenneth at whitecape.org> writes:
> 
> > Geminilake requires the 3D driver to select whether barriers are
> > intended for compute shaders, or tessellation control shaders, by
> > whacking a "Barrier Mode" bit in SLICE_COMMON_ECO_CHICKEN1 when
> > switching pipelines.  Failure to do this properly can result in GPU
> > hangs.
> >
> > Unfortunately, this means it needs to switch mid-batch, so only
> > userspace can properly set it.  To facilitate this, the kernel needs
> > to whitelist the register.
> >
> > The workarounds page currently tags this as applying to Broxton only,
> > but that doesn't make sense.  The documentation for the register it
> > references says the bit userspace is supposed to toggle only exists on
> > Geminilake.  Empirically, the Mesa patch to toggle this bit appears to
> > fix intermittent GPU hangs in tessellation control shader barrier tests
> > on Geminilake; we haven't seen those hangs on Broxton.
> >
> > v2: Mention WA #0862 in the comment (it doesn't have a name).
> >
> > Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> > Acked-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > Cc: stable at vger.kernel.org
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h        | 2 ++
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
> >  2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 966e4df9700e..505c605eff98 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7079,6 +7079,8 @@ enum {
> >  #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
> >  #define  DISABLE_PIXEL_MASK_CAMMING		(1<<14)
> >  
> > +#define GEN9_SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731c)
> > +
> >  #define GEN7_L3SQCREG1				_MMIO(0xB010)
> >  #define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index ebdcbcbacb3c..6bb51a502b8b 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1338,6 +1338,11 @@ static int glk_init_workarounds(struct intel_engine_cs *engine)
> >  	if (ret)
> >  		return ret;
> >  
> > +	/* WA #0862: Userspace has to set "Barrier Mode" to avoid hangs. */
> > +	ret = wa_ring_whitelist_reg(engine, GEN9_SLICE_COMMON_ECO_CHICKEN1);
> > +	if (ret)
> > +		return ret;
> > +
> >  	/* WaToEnableHwFixForPushConstHWBug:glk */
> >  	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> >  			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> > -- 
> > 2.15.1