[Intel-gfx] [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7

[Maarten Lankhorst]

Op 07-01-18 om 10:59 schreef Vidya Srinivas:
> From: Mahesh Kumar <mahesh1.kumar at intel.com>
>
> Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
> Hardware sometimes fails to wake memory from pkg C states fetching the
> last few lines of planar YUV 420 (NV12) planes. This causes
> intermittent underflow and corruption.
> WA: Disable package C states or do not enable latency levels 1 through 7
> (WM1 - WM7) on NV12 planes.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d75fd3b..90aa216 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4610,6 +4610,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>  		}
>  	}
>  
> +	/*
> +	 * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
> +	 * disable wm level 1-7 on NV12 planes
> +	 */
> +	if (wp->is_nv12 && level && (IS_SKYLAKE(dev_priv) ||
For clarity, might be better to do explicitly level >= 1 here, and move IS_SKYLAKE to a newline for better indent. :)

Otherwise looks good, so with that fixed you can add my r-b..
> +			IS_BROXTON(dev_priv) ||
> +			IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
> +		result->plane_en = false;
> +		return 0;
> +	}
> +
>  	result->plane_res_b = res_blocks;
>  	result->plane_res_l = res_lines;
>  	result->plane_en = true;