[Intel-gfx] [PATCH 05/27] drm/i915/icl: Show interrupt registers in debugfs

[Paulo Zanoni]

Em Qua, 2018-01-10 às 09:02 +0000, Tvrtko Ursulin escreveu:
> On 09/01/2018 23:23, Paulo Zanoni wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > 
> > v2: Update for POR changes. (Daniele Ceraolo Spurio)
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio at intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c | 82
> > ++++++++++++++++++++++++++++++++++++-
> >   1 file changed, 81 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 2bb63073d73f..e66318e1f76e 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -702,6 +702,64 @@ static int i915_interrupt_info(struct seq_file
> > *m, void *data)
> >   				   i, I915_READ(GEN8_GT_IER(i)));
> >   		}
> >   
> > +		seq_printf(m, "PCU interrupt mask:\t%08x\n",
> > +			   I915_READ(GEN8_PCU_IMR));
> > +		seq_printf(m, "PCU interrupt identity:\t%08x\n",
> > +			   I915_READ(GEN8_PCU_IIR));
> > +		seq_printf(m, "PCU interrupt enable:\t%08x\n",
> > +			   I915_READ(GEN8_PCU_IER));
> 
> ^^^ This looks dodgy, like it was butchered by the auto-rebaser, vvv
> ?

With the patch applied, both the CHV and the ICL branches of the if
statement include these 3 seq_printf() calls.

The patch is "adding" these printfs to the CHV part of the if, but if
you see below it "moves" the printfs that were originally part of CHV
to ICL. I think it's just a case of diff organizing things in a
different way than a human would.

Now, if we don't want to print these things on ICL too, then that's an
error.

> 
> Tvrtko
> 
> > +	} else if (INTEL_GEN(dev_priv) >= 11) {
> > +		seq_printf(m, "Master Interrupt Control:  %08x\n",
> > +			   I915_READ(GEN11_GFX_MSTR_IRQ));
> > +
> > +		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
> > +			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE
> > ));
> > +		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
> > +			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
> > +		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
> > +			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
> > +		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
> > +			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENAB
> > LE));
> > +		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
> > +			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE
> > ));
> > +		seq_printf(m, "GUnit/CSME Intr
> > Enable:\t   %08x\n",
> > +			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE)
> > );
> > +
> > +		seq_printf(m, "Display Interrupt
> > Control:\t%08x\n",
> > +			   I915_READ(GEN11_DISPLAY_INT_CTL));
> > +
> > +		for_each_pipe(dev_priv, pipe) {
> > +			if
> > (!intel_display_power_is_enabled(dev_priv,
> > +						POWER_DOMAIN_PIPE(
> > pipe))) {
> > +				seq_printf(m, "Pipe %c power
> > disabled\n",
> > +					   pipe_name(pipe));
> > +				continue;
> > +			}
> > +			seq_printf(m, "Pipe %c IMR:\t%08x\n",
> > +				   pipe_name(pipe),
> > +				   I915_READ(GEN8_DE_PIPE_IMR(pipe
> > )));
> > +			seq_printf(m, "Pipe %c IIR:\t%08x\n",
> > +				   pipe_name(pipe),
> > +				   I915_READ(GEN8_DE_PIPE_IIR(pipe
> > )));
> > +			seq_printf(m, "Pipe %c IER:\t%08x\n",
> > +				   pipe_name(pipe),
> > +				   I915_READ(GEN8_DE_PIPE_IER(pipe
> > )));
> > +		}
> > +
> > +		seq_printf(m, "Display Engine port interrupt
> > mask:\t%08x\n",
> > +			   I915_READ(GEN8_DE_PORT_IMR));
> > +		seq_printf(m, "Display Engine port interrupt
> > identity:\t%08x\n",
> > +			   I915_READ(GEN8_DE_PORT_IIR));
> > +		seq_printf(m, "Display Engine port interrupt
> > enable:\t%08x\n",
> > +			   I915_READ(GEN8_DE_PORT_IER));
> > +
> > +		seq_printf(m, "Display Engine misc interrupt
> > mask:\t%08x\n",
> > +			   I915_READ(GEN8_DE_MISC_IMR));
> > +		seq_printf(m, "Display Engine misc interrupt
> > identity:\t%08x\n",
> > +			   I915_READ(GEN8_DE_MISC_IIR));
> > +		seq_printf(m, "Display Engine misc interrupt
> > enable:\t%08x\n",
> > +			   I915_READ(GEN8_DE_MISC_IER));
> > +
> >   		seq_printf(m, "PCU interrupt mask:\t%08x\n",
> >   			   I915_READ(GEN8_PCU_IMR));
> >   		seq_printf(m, "PCU interrupt identity:\t%08x\n",
> > @@ -845,13 +903,35 @@ static int i915_interrupt_info(struct
> > seq_file *m, void *data)
> >   		seq_printf(m, "Graphics Interrupt mask:		
> > %08x\n",
> >   			   I915_READ(GTIMR));
> >   	}
> > -	if (INTEL_GEN(dev_priv) >= 6) {
> > +
> > +	if (INTEL_GEN(dev_priv) >= 11) {
> > +		seq_printf(m, "RCS Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
> > +		seq_printf(m, "BCS Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
> > +		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
> > +		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
> > +		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK))
> > ;
> > +		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_GUC_SG_INTR_MASK));
> > +		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
> > +			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK
> > ));
> > +		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK))
> > ;
> > +		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
> > +			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
> > +
> > +	} else if (INTEL_GEN(dev_priv) >= 6) {
> >   		for_each_engine(engine, dev_priv, id) {
> >   			seq_printf(m,
> >   				   "Graphics Interrupt mask (%s):
> > 	%08x\n",
> >   				   engine->name,
> > I915_READ_IMR(engine));
> >   		}
> >   	}
> > +
> >   	intel_runtime_pm_put(dev_priv);
> >   
> >   	return 0;
> >