[Intel-gfx] [PATCH 10/27] drm/i915/icl: Enhanced execution list support

[Daniele Ceraolo Spurio]

The review from Chris had ended up in my spam folder and I missed it, 
apologies for duplicating some of the comments.

Daniele

On 11/01/18 11:55, Daniele Ceraolo Spurio wrote:
> 
> 
> On 09/01/18 15:28, Paulo Zanoni wrote:
>> From: Thomas Daniel <thomas.daniel at intel.com>
>>
>> Supports two-element submission using the new enhanced execlist mechanism
>>
> 
> This could use a few lines to describe enhanced execlist. Something like:
> 
> "Enhanced Execlists is an upgraded version of execlists which supports 
> up to 8 ports. The lrcs to be submitted are written to a submit queue, 
> which is then loaded on the HW. When writing to the ELSP register, the 
> lrcs are written cyclically in the queue from position 0 to position 7. 
> Alternatively, it is possible to write directly in the individual 
> positions of the queue using the ELSQ registers. To be able to re-use 
> all the existing code we're using the latter method and we're currently 
> limiting ourself to only using 2 elements"
> 
>> v2: Rebase.
>> v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
>> v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
>>
>> Signed-off-by: Thomas Daniel <thomas.daniel at intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_lrc.c | 21 ++++++++++++++++++++-
>>   drivers/gpu/drm/i915/intel_lrc.h |  3 +++
>>   2 files changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
>> b/drivers/gpu/drm/i915/intel_lrc.c
>> index de41ad2d5fbc..3c6f587fa903 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -430,9 +430,18 @@ static inline void elsp_write(u64 desc, u32 
>> __iomem *elsp)
>>   static void execlists_submit_ports(struct intel_engine_cs *engine)
>>   {
>> +    struct drm_i915_private *dev_priv = engine->i915;
>>       struct execlist_port *port = engine->execlists.port;
>> +    u32 __iomem *elsq =
>> +        engine->i915->regs + i915_mmio_reg_offset(RING_ELSQ(engine));
> 
> Should we cache this, like we do for execlists.elsp?
> 
>>       unsigned int n;
>> +    /*
>> +     * Gen11+ note: the submit queue is not cleared after being 
>> submitted
>> +     * to the HW so we need to make sure we always clean it up. This is
>> +     * currently ensured by the fact that we always write the same 
>> number
>> +     * of elsq entries, keep this in mind before changing the loop 
>> below.
>> +     */
>>       for (n = execlists_num_ports(&engine->execlists); n--; ) {
>>           struct drm_i915_gem_request *rq;
>>           unsigned int count;
>> @@ -456,8 +465,18 @@ static void execlists_submit_ports(struct 
>> intel_engine_cs *engine)
>>               desc = 0;
>>           }
>> -        elsp_write(desc, engine->execlists.elsp);
>> +        if (INTEL_GEN(engine->i915) >= 11) {
>> +            writel(lower_32_bits(desc), elsq + n * 2);
>> +            writel(upper_32_bits(desc), elsq + n * 2 + 1);
>> +        } else {
>> +            elsp_write(desc, engine->execlists.elsp);
>> +        }
>>       }
>> +
>> +    /* for gen11+ we need to manually load the submit queue */
>> +    if (INTEL_GEN(engine->i915) >= 11)
>> +        I915_WRITE_FW(RING_ELCR(engine), ELCR_LOAD);
>> +
>>       execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
>>   }
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.h 
>> b/drivers/gpu/drm/i915/intel_lrc.h
>> index 6d4f9b995a11..cb00e1dd6ed2 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.h
>> +++ b/drivers/gpu/drm/i915/intel_lrc.h
>> @@ -38,6 +38,9 @@
>>   #define      CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT    (1 << 0)
>>   #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
>>   #define RING_CONTEXT_STATUS_BUF_BASE(engine)    
>> _MMIO((engine)->mmio_base + 0x370)
>> +#define RING_ELSQ(engine)            _MMIO((engine)->mmio_base + 0x510)
>> +#define RING_ELCR(engine)            _MMIO((engine)->mmio_base + 0x550)
> 
> Do we need to add the new regs to the forcewake domain identification in 
> logical_ring_setup? They should be in the same well as ELSP so maybe 
> just that one is enough.
> 
>> +#define      ELCR_LOAD                (1 << 0) >   #define 
>> RING_CONTEXT_STATUS_BUF_LO(engine, i) 
> _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
>>   #define RING_CONTEXT_STATUS_BUF_HI(engine, i)    
>> _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
>>   #define RING_CONTEXT_STATUS_PTR(engine)        
>> _MMIO((engine)->mmio_base + 0x3a0)
>>
> 
> Side note, we do have pre-emption enabled in the features but this patch 
> does not update inject_preempt_context to use the new way to submit to 
> the HW, so I guess that's probably break.
> 
> Daniele
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx