[Intel-gfx] [PATCH] drm/i915/cnl: apply Display WA #1178 to fix type C dongles

[Rodrigo Vivi]

On Thu, Jan 18, 2018 at 07:39:51PM +0000, Rodrigo Vivi wrote:
> On Tue, Nov 28, 2017 at 10:05:53PM +0000, Lucas De Marchi wrote:
> > Display WA #1178 is meant to fix Aux channel voltage swing too low with
> > some type C dongles. Although it is for type C, HW engineers reported
> > that it can be applied to all external ports even if they are not going
> > to type C.
> > 
> > For CNL we apply the workaround every time Aux B, C and D are powering
> > up since they will lose the configuration when powered down.
> > 
> > v2: Use common tag for WA
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > Cc: Arthur J Runyan <arthur.j.runyan at intel.com>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> 
> we got all confirmations that we need. Thanks Art.
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

merged. Thanks for the patch.

> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         | 11 +++++++++++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |  9 +++++++++
> >  2 files changed, 20 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 09bf043c1c2e..0214327d8af7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8335,6 +8335,17 @@ enum skl_power_gate {
> >  #define  SKL_PW_TO_PG(pw)			((pw) - SKL_DISP_PW_1 + SKL_PG1)
> >  #define  SKL_FUSE_PG_DIST_STATUS(pg)		(1 << (27 - (pg)))
> >  
> > +#define _CNL_AUX_REG_IDX(pw)		((pw - 1) >> 4)
> > +#define _CNL_AUX_ANAOVRD1_B		0x162250
> > +#define _CNL_AUX_ANAOVRD1_C		0x162210
> > +#define _CNL_AUX_ANAOVRD1_D		0x1622D0
> > +#define CNL_AUX_ANAOVRD1(pw)		_MMIO(_PICK(_CNL_AUX_REG_IDX(pw), \
> > +						    _CNL_AUX_ANAOVRD1_B, \
> > +						    _CNL_AUX_ANAOVRD1_C, \
> > +						    _CNL_AUX_ANAOVRD1_D))
> > +#define   CNL_AUX_ANAOVRD1_ENABLE	(1<<16)
> > +#define   CNL_AUX_ANAOVRD1_LDO_BYPASS	(1<<23)
> > +
> >  /* Per-pipe DDI Function Control */
> >  #define _TRANS_DDI_FUNC_CTL_A		0x60400
> >  #define _TRANS_DDI_FUNC_CTL_B		0x61400
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 8315499452dc..29f14e724f41 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -388,6 +388,15 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> >  	I915_WRITE(HSW_PWR_WELL_CTL_DRIVER(id), val | HSW_PWR_WELL_CTL_REQ(id));
> >  	hsw_wait_for_power_well_enable(dev_priv, power_well);
> >  
> > +	/* Display WA #1178: cnl */
> > +	if (IS_CANNONLAKE(dev_priv) &&
> > +	    (id == CNL_DISP_PW_AUX_B || id == CNL_DISP_PW_AUX_C ||
> > +	     id == CNL_DISP_PW_AUX_D)) {
> > +		val = I915_READ(CNL_AUX_ANAOVRD1(id));
> > +		val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS;
> > +		I915_WRITE(CNL_AUX_ANAOVRD1(id), val);
> > +	}
> > +
> >  	if (wait_fuses)
> >  		gen9_wait_for_power_well_fuses(dev_priv, pg);
> >  
> > -- 
> > 2.14.3
> > 
> > _______________________________________________
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