[Intel-gfx] [PATCH 1/2] drm/i915: Increase render/media power gating hysteresis for gen9+

[Sagar Arun Kamble]

On 1/20/2018 3:01 PM, Chris Wilson wrote:
> On gen9+, after an idle period the HW will disable the entire power well
> to conserve power (by preventing current leakage). It takes around a 100
> microseconds to bring the power well back online afterwards. With the
> current hysteresis value of 25us, we do not have sufficient time to
> respond to an interrupt and schedule the next execution before the HW
> powers itself down. (At present, we prevent this by grabbing the
> forcewake for prolonged periods of time, but that is overkill fixed in
> the next patch.) The minimum we want to set the power gating hysteresis
> to is the length of time it takes us to service the GPU, which across a
> broad spectrum of machines is about 250us.
>
> (Note this also brings guc latency into the same ballpark as execlists.)
>
> Testcase: igt/gem_exec_nop/sequential
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> Cc: Michel Thierry <michel.thierry at intel.com>
> Cc: Michal Winiarski <michal.winiarski at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1db79a860b96..6748d3efb537 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6627,8 +6627,8 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
>   	I915_WRITE(GEN6_RC_SLEEP, 0);
>   
>   	/* 2c: Program Coarse Power Gating Policies. */
> -	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
> -	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
> +	I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
> +	I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
As per bspec this is in 1.28usec units so it should be 195.
With that:
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
>   
>   	/* 3a: Enable RC6 */
>   	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */