[Intel-gfx] [PATCH] drm/i915/cnl: Fix DP max rate for Cannonlake with port F.

[Manasi Navare]

On Tue, Jan 23, 2018 at 02:32:57PM -0800, Rodrigo Vivi wrote:
> On CNL SKUs that uses port F,  max DP rate is 8.1G for all
> ports when we have the elevated voltage.
>

Just a nit here on the commit message. Would it make more sense
to mention the elevated voltage numerical value instead of just
elevated voltage?

Other than that the rate selection logic is correct.

Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>

Manasi
 
> v2: Make commit message more generic.
> v3: Move conditions to a helper to get easier to read. (Ville).
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Manasi Navare <manasi.d.navare at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 29 ++++++++++++++++++++++-------
>  1 file changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 2b26ffe100b1..31a968f20761 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -220,15 +220,34 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
>  	return max_dotclk;
>  }
>  
> +static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	enum port port = dig_port->base.port;
> +
> +	u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> +
> +	/* Low voltage SKUs are limited to max of 5.4G */
> +	if (voltage == VOLTAGE_INFO_0_85V)
> +		return size - 2;
> +
> +	/* For this SKU 8.1G is supported in all ports */
> +	if(IS_CNL_WITH_PORT_F(dev_priv))
> +		return size;
> +
> +	/* For other SKUs, max rate on ports A and B is 5.4G */
> +	if (port == PORT_A || port == PORT_D)
> +		return size - 2;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> -	enum port port = dig_port->base.port;
>  	const int *source_rates;
>  	int size;
> -	u32 voltage;
>  
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -238,11 +257,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		size = ARRAY_SIZE(bxt_rates);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		source_rates = cnl_rates;
> -		size = ARRAY_SIZE(cnl_rates);
> -		voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
> -		if (port == PORT_A || port == PORT_D ||
> -		    voltage == VOLTAGE_INFO_0_85V)
> -			size -= 2;
> +		size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
> -- 
> 2.13.6
>