[Intel-gfx] [PATCH] drm/i915/cnl: WaPipeControlBefore3DStateSamplePattern

[Chris Wilson]

Quoting Rafael Antognolli (2018-01-26 01:26:34)
> Write a PIPE_CONTROL with CS stall followed by 14 dwords of 0 in the
> indirect context wa bb.

14 MI_NOOPS following? That isn't what you wrote in the code, but the
main thing you haven't explained is why. A normal batch will already
have a flush in its setup, but more to the point would be the only
reason this is required is because of an implicit 3DSTATE inside the
context image on preemption. Right? Otherwise it seems to be a purely
userspace problem.
-Chris