[Intel-gfx] [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init

[Paulo Zanoni]

Em Ter, 2018-01-23 às 16:49 -0800, James Ausmus escreveu:
> On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> > From: Mahesh Kumar <mahesh1.kumar at intel.com>
> > 
> > ICL has 2 slices of DBuf, enable both the slices during display
> > init.
> > 
> > Ideally we should only enable the second slice when needed in order
> > to
> > save power, but while we're not there yet, adopt the simpler
> > solution
> > to keep us bug-free.
> > 
> > v2 (from Paulo):
> >   - Add the TODO comment.
> >   - Reorganize where things are defined.
> >   - Fix indentation.
> >   - Remove unnecessary POSTING_READ() calls.
> >   - Improve the commit message.
> > 
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         |  2 ++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 34
> > +++++++++++++++++++++++++++++++--
> >  2 files changed, 34 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 979bc06a59f4..1746df9a263d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7122,6 +7122,8 @@ enum {
> >  #define  DISP_DATA_PARTITION_5_6	(1<<6)
> >  #define  DISP_IPC_ENABLE		(1<<3)
> >  #define DBUF_CTL	_MMIO(0x45008)
> > +#define DBUF_CTL_S1	_MMIO(0x45008)
> 
> Since it's the exact same register, is it really worth duplicating,
> or
> should we just use the existing DBUF_CTL instead of adding
> DBUF_CTL_S1?

I like it: it's just a single extra line on i915_reg.h and adds clarity
to the code that uses it. But I have nothing against removing it too.


> 
> 
> > +#define DBUF_CTL_S2	_MMIO(0x44FE8)
> >  #define  DBUF_POWER_REQUEST		(1<<31)
> >  #define  DBUF_POWER_STATE		(1<<30)
> >  #define GEN7_MSG_CTL	_MMIO(0x45010)
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 2556db16c76a..7801a425398f 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct
> > drm_i915_private *dev_priv)
> >  		DRM_ERROR("DBuf power disable timeout!\n");
> >  }
> >  
> > +/*
> > + * TODO: we shouldn't always enable DBUF_CTL_S2, we should only
> > enable it when
> > + * needed and keep it disabled as much as possible.
> > + */
> > +static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> > +{
> > +	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) |
> > DBUF_POWER_REQUEST);
> > +	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) |
> > DBUF_POWER_REQUEST);
> > +	POSTING_READ(DBUF_CTL_S2);
> > +
> > +	udelay(10);
> 
> BSpec says to poll, and timeout/fail after 10 uS, rather than
> unconditionally busy wait - worth making more complex to potentially
> save a few uS of busy wait?

Yeah, good points. We have intel_wait_for_register() to help avoid the
complexity here.


> 
> > +
> > +	if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> > +	    !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > +		DRM_ERROR("DBuf power enable timeout\n");
> > +}
> > +
> > +static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> > +{
> > +	I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) &
> > ~DBUF_POWER_REQUEST);
> > +	I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) &
> > ~DBUF_POWER_REQUEST);
> > +	POSTING_READ(DBUF_CTL_S2);
> > +
> > +	udelay(10);
> > +
> > +	if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> > +	    (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> > +		DRM_ERROR("DBuf power disable timeout!\n");
> > +}
> > +
> >  static void skl_display_core_init(struct drm_i915_private
> > *dev_priv,
> >  				   bool resume)
> >  {
> > @@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct
> > drm_i915_private *dev_priv,
> >  	icl_init_cdclk(dev_priv);
> >  
> >  	/* 6. Enable DBUF. */
> > -	gen9_dbuf_enable(dev_priv);
> > +	icl_dbuf_enable(dev_priv);
> >  
> >  	/* 7. Setup MBUS. */
> >  	/* FIXME: MBUS code not here yet. */
> > @@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct
> > drm_i915_private *dev_priv)
> >  	/* 1. Disable all display engine functions -> aready done
> > */
> >  
> >  	/* 2. Disable DBUF */
> > -	gen9_dbuf_disable(dev_priv);
> > +	icl_dbuf_disable(dev_priv);
> >  
> >  	/* 3. Disable CD clock */
> >  	icl_uninit_cdclk(dev_priv);
> > -- 
> > 2.14.3
> > 
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