[Intel-gfx] [PATCH 0/9] ICL mergeable patches

[Paulo Zanoni]

These patches were part of the other ICL series that arrived on the
list a few days ago, they already received public reviews. They should
be good to go, but let's see what the CI system has to say about them
first.

James Ausmus (1):
  drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field

Kelvin Gardiner (1):
  drm/i915/icl: Set graphics mode register for gen11

Mahesh Kumar (5):
  drm/i915/icl: Don't allocate fixed bypass path blocks for ICL
  drm/i915/icl: Do not fix dbuf block size to 512
  drm/i915/icl: Fail flip if ddb allocated are less than min display
    buffer needed
  drm/i915/icl: NV12 y-plane ddb is not in same plane
  drm/i915/icl: Introduce MBus related registers

Paulo Zanoni (2):
  drm/i915/gen11: fix the SAGV block time for gen11
  drm/i915/icl: allow the reg_read ioctl to read the RCS TIMESTAMP
    register

 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/i915_reg.h      | 33 +++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c |  5 ++-
 drivers/gpu/drm/i915/intel_lrc.c     | 18 ++++++++--
 drivers/gpu/drm/i915/intel_pm.c      | 69 +++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_uncore.c  |  2 +-
 6 files changed, 112 insertions(+), 16 deletions(-)

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2.14.3