[Intel-gfx] [PATCH 2/2] drm/i915: write fence reg only once on VGPU

[Zhao Yakui]

On VGPU scenario the read/write operation of fence_reg will be trapped
by the GVT-g. And then gvt-g follows the HW spec to write the fence_reg.
So it is unnecessary to read/write fence reg several times. This will help
to reduce the unnecessary trap of fence_reg mmio operation.

Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d92fe03..55bf6d9 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -95,11 +95,15 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
 
 	if (INTEL_GEN(fence->i915) >= 6) {
 		/* Use the 64-bit RW to read/write fence reg on SNB+ */
-		I915_WRITE64_FW(fence_reg_lo, 0);
-		I915_READ64(fence_reg_lo);
-
-		I915_WRITE64_FW(fence_reg_lo, val);
-		I915_READ64(fence_reg_lo);
+		if (intel_vgpu_active(i915))
+			I915_WRITE64_FW(fence_reg_lo, val);
+		else {
+			I915_WRITE64_FW(fence_reg_lo, 0);
+			I915_READ64(fence_reg_lo);
+
+			I915_WRITE64_FW(fence_reg_lo, val);
+			I915_READ64(fence_reg_lo);
+		}
 	} else {
 		/* To w/a incoherency with non-atomic 64-bit register updates,
 		 * we split the 64-bit update into two 32-bit writes. In order
-- 
2.7.4