[Intel-gfx] [PATCH v2 2/2] drm/i915: write fence reg only once on VGPU

[Daniel Vetter]

On Tue, Jul 03, 2018 at 10:56:17AM +0800, Zhao Yakui wrote:
> On VGPU scenario the read/write operation of fence_reg will be trapped
> by the GVT-g. And then gvt-g follows the HW spec to write the fence_reg.
> So it is unnecessary to read/write fence reg several times. This will help
> to reduce the unnecessary trap of fence_reg mmio operation.
> 
> V1->V2: Fix one typo error of parameter when calling intel_vgpu_active
> 
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>

Ok this makes more sense. Except you need to put the 64bit entirely into
the vpgu block, with a comment explaining why this is safe (since the vpgu
will take care of updating fences correctly).
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_gem_fence_reg.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index d92fe03..9c97976 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -95,11 +95,15 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
>  
>  	if (INTEL_GEN(fence->i915) >= 6) {
>  		/* Use the 64-bit RW to read/write fence reg on SNB+ */
> -		I915_WRITE64_FW(fence_reg_lo, 0);
> -		I915_READ64(fence_reg_lo);
> -
> -		I915_WRITE64_FW(fence_reg_lo, val);
> -		I915_READ64(fence_reg_lo);
> +		if (intel_vgpu_active(dev_priv))
> +			I915_WRITE64_FW(fence_reg_lo, val);
> +		else {
> +			I915_WRITE64_FW(fence_reg_lo, 0);
> +			I915_READ64(fence_reg_lo);
> +
> +			I915_WRITE64_FW(fence_reg_lo, val);
> +			I915_READ64(fence_reg_lo);
> +		}
>  	} else {
>  		/* To w/a incoherency with non-atomic 64-bit register updates,
>  		 * we split the 64-bit update into two 32-bit writes. In order
> -- 
> 2.7.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch