[Intel-gfx] [PATCH v2 1/2] drm/i915: Use 64-bit to Read/Write fence reg on SNB+

[Zhao, Yakui]

>-----Original Message-----
>From: Chris Wilson [mailto:chris at chris-wilson.co.uk]
>Sent: Tuesday, July 3, 2018 5:01 PM
>To: Daniel Vetter <daniel at ffwll.ch>; Zhao, Yakui <yakui.zhao at intel.com>
>Cc: intel-gfx at lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Use 64-bit to Read/Write
>fence reg on SNB+
>
>Quoting Daniel Vetter (2018-07-03 09:49:29)
>> On Tue, Jul 03, 2018 at 10:56:16AM +0800, Zhao Yakui wrote:
>> > Based on HW spec the fence reg on SNB+ is defined as 64-bit. Just
>> > follow the b-spec to  use 64-bit read/write mode.
>> >
>> > Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
>>
>> Please use git blame to understand why you've just re-introduced a bug
>> that took months to debug.
>
>And there's even a very nice comment explaining exactly what the HW does
>and why the double write is required.
>
>First rule of IT: turn if off and on again.

Hi, Chris/Daniel

       Thanks for the detailed explanation.  I check the history of this issue.  It was one commit about five years ago.
Maybe the op of fence reg on HW doesn't follow its description very strictly. Not sure whether it is changed on the latest HW.  
        OK. Please ignore this patch as the double write is safer.

>-Chris