[Intel-gfx] [PATCH v3] drm/i915: Use 64-bit write to optimize writing fence_reg on VGPU

[Chris Wilson]

Quoting Zhao Yakui (2018-07-03 14:27:47)
> On VGPU scenario the read/write operation of fence_reg will be trapped
> by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg.
> And the gvt-g takes care of updating the fence reg correctly for any
> trapped value of fence reg.
> 
> So it is unnecessary to read/write fence reg several times. It is enough 
> that the fence reg is written only value in 64-bit mdoe. This will help
> to reduce the redundantt trap of fence_reg mmio operation.
> 
> V1->V2: Fix one typo error of parameter when calling intel_vgpu_active.
> V2->V3: Follow Chris Wilson and Daniel Vetter to add more descriptions.
> 
> Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_fence_reg.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> index d548ac0..7b10bf9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> @@ -63,6 +63,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
>         i915_reg_t fence_reg_lo, fence_reg_hi;
>         int fence_pitch_shift;
>         u64 val;
> +       struct drm_i915_private *dev_priv = fence->i915;
>  
>         if (INTEL_GEN(fence->i915) >= 6) {
>                 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
> @@ -92,9 +93,17 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence,
>                 val |= I965_FENCE_REG_VALID;
>         }
>  
> -       if (!pipelined) {
> -               struct drm_i915_private *dev_priv = fence->i915;

Ahem.
-Chris