[Intel-gfx] ✓ Fi.CI.BAT: success for ICELAKE DSI DRIVER (rev2)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev2)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4423 -> Patchwork_9509 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9509 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt at kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         NOTRUN -> INCOMPLETE (fdo#103927)

    
    ==== Possible fixes ====

    igt at gem_exec_suspend@basic-s3:
      {fi-cfl-8109u}:     INCOMPLETE -> PASS

    igt at kms_chamelium@dp-edid-read:
      fi-kbl-7500u:       FAIL (fdo#103841) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927


== Participating hosts (45 -> 41) ==

  Additional (1): fi-bxt-dsi 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4423 -> Patchwork_9509

  CI_DRM_4423: 9b9b45349fe3a36d41586992426d03a238396531 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4533: 199220052af977598033d3810ffb4cc32d377522 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9509: cd40dd3bd2598cdfec11b40ea20f131ac7744690 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

cd40dd3bd259 drm/i915/icl: Configure DSI transcoders
114939859df1 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
9ef3b3bf6808 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
c7b18a81b3c5 drm/i915/icl: Get DSI transcoder for a given port
4760909d3125 drm/i915/icl: Program TA_TIMING_PARAM registers
a9e9217a3bd3 drm/i915/icl: Define TA_TIMING_PARAM registers
17de6721e0a6 drm/i915/icl: Program DSI clock and data lane timing params
a3ec308da955 drm/i915/icl: Define data/clock lanes dphy timing registers
8f2580e74e6e drm/i915/icl: Program T_INIT_MASTER registers
bcc53825cc97 drm/i915/icl: Define T_INIT_MASTER registers
3dda606aeffa drm/i915/icl: Enable DDI Buffer
4e884239f1e1 drm/i915/icl: DSI vswing programming sequence
9f6dbc7b8083 drm/i915/icl: Configure lane sequencing of combo phy transmitter
3338fcea233b drm/i915/icl: Define AUX lane registers for Port A/B
c03cde1bb29b drm/i915/icl: Power down unused DSI lanes
a5a0e7ef8798 drm/i915/icl: Define PORT_CL_DW_10 register
f42b0a7ec096 drm/i915/icl: Enable DSI IO power
bd698aa15977 drm/i915/icl: Define DSI mode ctl register
5d1f14446c69 drm/i915/icl: Program DSI Escape clock Divider
2fb3a21077c4 drm/i915/icl: Define register for DSI PLL

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9509/issues.html