[Intel-gfx] [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, July 4, 2018 8:08 PM
> To: Chauhan, Madhav <madhav.chauhan at intel.com>; intel-
> gfx at lists.freedesktop.org
> Cc: Vivi, Rodrigo <rodrigo.vivi at intel.com>; Zanoni, Paulo R
> <paulo.r.zanoni at intel.com>; Shankar, Uma <uma.shankar at intel.com>;
> Chauhan, Madhav <madhav.chauhan at intel.com>
> Subject: Re: [PATCH v2 05/20] drm/i915/icl: Define PORT_CL_DW_10 register
> 
> On Tue, 03 Jul 2018, Madhav Chauhan <madhav.chauhan at intel.com>
> wrote:
> > This register used to power down individual lanes for DDI/DSI ports.
> > Bitfields to power up/down various combinations of lanes are also
> > added in this patch.
> >
> > v2: Review comments from Jani N
> >     - Use override instead of "override" for bitfields
> >     - Define mask for override bitfield
> >     - Define PWR_DOWN_LN* macros shifted in place
> >
> > Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index dfd603c..3fa8f02 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1704,6 +1704,26 @@ enum i915_power_well_id {
> >  #define ICL_PORT_CL_DW5(port)	_MMIO_PORT(port,
> _ICL_PORT_CL_DW5_A, \
> >  						 _ICL_PORT_CL_DW5_B)
> >
> > +#define _CNL_PORT_CL_DW10_A		0x162028
> > +#define _ICL_PORT_CL_DW10_B		0x6c028
> > +#define ICL_PORT_CL_DW10(port)		_MMIO_PORT(port,	\
> > +						   _CNL_PORT_CL_DW10_A, \
> > +						   _ICL_PORT_CL_DW10_B)
> > +#define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
> > +#define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
> > +#define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
> > +#define  PWR_UP_ALL_LANES		(0x0 << 4)
> > +#define  PWR_DOWN_LN_3_2_1		(0xe << 4)
> > +#define  PWR_DOWN_LN_3_2		(0xc << 4)
> > +#define  PWR_DOWN_LN_3			(0x8 << 4)
> > +#define  PWR_DOWN_LN_2_1_0		(0x7 << 4)
> > +#define  PWR_DOWN_LN_1_0		(0x3 << 4)
> > +#define  PWR_DOWN_LN_1			(0x2 << 4)
> > +#define  PWR_DOWN_LN_3_1		(0xa << 4)
> > +#define  PWR_DOWN_LN_3_1_0		(0xb << 4)
> > +#define  PWR_DOWN_LN_MASK		(0xf0 << 4)
> 
> Should be (0xf << 4).

Right, my bad. Will fix it in next version.

Regards,
Madhav

> 
> With that fixed,
> 
> Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> 
> 
> > +#define  PWR_DOWN_LN_SHIFT		4
> > +
> >  #define _PORT_CL1CM_DW9_A		0x162024
> >  #define _PORT_CL1CM_DW9_BC		0x6C024
> >  #define   IREF0RC_OFFSET_SHIFT		8
> 
> --
> Jani Nikula, Intel Open Source Graphics Center