[Intel-gfx] [PATCH v4 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers

[Madhav Chauhan]

This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4be18e9..72dac21 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10059,6 +10059,46 @@ enum skl_power_gate {
 						   _ICL_DSI_T_INIT_MASTER_0,\
 						   _ICL_DSI_T_INIT_MASTER_1)
 
+#define _DPHY_CLK_TIMING_PARAM_0	0x162180
+#define _DPHY_CLK_TIMING_PARAM_1	0x6c180
+#define DPHY_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_CLK_TIMING_PARAM_0,\
+						   _DPHY_CLK_TIMING_PARAM_1)
+#define _DSI_CLK_TIMING_PARAM_0		0x6b080
+#define _DSI_CLK_TIMING_PARAM_1		0x6b880
+#define DSI_CLK_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_CLK_TIMING_PARAM_0,\
+						   _DSI_CLK_TIMING_PARAM_1)
+#define  CLK_PREP_OVERRIDE		(1 << 31)
+#define  CLK_PREP_TIME(x)		(x << 28)
+#define  CLK_ZERO_OVERRIDE		(1 << 27)
+#define  CLK_ZERO_TIME(x)		(x << 20)
+#define  CLK_PRE_OVERRIDE		(1 << 19)
+#define  CLK_PRE_TIME(x)		(x << 16)
+#define  CLK_POST_OVERRIDE		(1 << 15)
+#define  CLK_POST_TIME(x)		(x << 8)
+#define  CLK_TRAIL_OVERRIDE		(1 << 7)
+#define  CLK_TRAIL_TIME(x)		(x << 0)
+
+#define _DPHY_DATA_TIMING_PARAM_0	0x162184
+#define _DPHY_DATA_TIMING_PARAM_1	0x6c184
+#define DPHY_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DPHY_DATA_TIMING_PARAM_0,\
+						   _DPHY_DATA_TIMING_PARAM_1)
+#define _DSI_DATA_TIMING_PARAM_0	0x6B084
+#define _DSI_DATA_TIMING_PARAM_1	0x6B884
+#define DSI_DATA_TIMING_PARAM(port)	_MMIO_PORT(port,	\
+						   _DSI_DATA_TIMING_PARAM_0,\
+						   _DSI_DATA_TIMING_PARAM_1)
+#define  HS_PREP_OVERRIDE		(1 << 31)
+#define  HS_PREP_TIME(x)		(x << 24)
+#define  HS_ZERO_OVERRIDE		(1 << 23)
+#define  HS_ZERO_TIME(x)		(x << 16)
+#define  HS_TRAIL_OVERRIDE		(1 << 15)
+#define  HS_TRAIL_TIME(x)		(x << 8)
+#define  HS_EXIT_OVERRIDE		(1 << 7)
+#define  HS_EXIT_TIME(x)		(x << 0)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL		(dev_priv->mipi_mmio_base + 0xb884)
-- 
2.7.4