[Intel-gfx] [PATCH] drm/i915: remove confusing GPIO vs PCH_GPIO
Lucas De Marchi
lucas.demarchi at intel.com
Fri Jul 6 04:58:13 UTC 2018
Instead of defining all registers twice, define just a PCH_GPIO_BASE
that has the same address as PCH_GPIO_A and use that to calculate all
the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
the same thing.
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
---
As discussed on https://patchwork.freedesktop.org/patch/225388/.
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 37 +++++++++++++++--------------
drivers/gpu/drm/i915/intel_i2c.c | 15 ++++++------
3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e39492aaff6c..e25a74fe753b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
gmbus_mmio_write);
- MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc953ee7e3b3..11503ed60832 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3045,18 +3045,6 @@ enum i915_power_well_id {
/*
* GPIO regs
*/
-#define GPIOA _MMIO(0x5010)
-#define GPIOB _MMIO(0x5014)
-#define GPIOC _MMIO(0x5018)
-#define GPIOD _MMIO(0x501c)
-#define GPIOE _MMIO(0x5020)
-#define GPIOF _MMIO(0x5024)
-#define GPIOG _MMIO(0x5028)
-#define GPIOH _MMIO(0x502c)
-#define GPIOJ _MMIO(0x5034)
-#define GPIOK _MMIO(0x5038)
-#define GPIOL _MMIO(0x503C)
-#define GPIOM _MMIO(0x5040)
# define GPIO_CLOCK_DIR_MASK (1 << 0)
# define GPIO_CLOCK_DIR_IN (0 << 1)
# define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -7625,12 +7613,25 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GPIOA _MMIO(0xc5010)
-#define PCH_GPIOB _MMIO(0xc5014)
-#define PCH_GPIOC _MMIO(0xc5018)
-#define PCH_GPIOD _MMIO(0xc501c)
-#define PCH_GPIOE _MMIO(0xc5020)
-#define PCH_GPIOF _MMIO(0xc5024)
+#define GPIO_OFFSET 0x5010u
+#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
+#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
+
+enum i915_gpio {
+ GPIOA = 0,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ GPIOH,
+ __GPIOI_UNUSED,
+ GPIOJ,
+ GPIOK,
+ GPIOL,
+ GPIOM,
+};
#define PCH_GMBUS0 _MMIO(0xc5100)
#define PCH_GMBUS1 _MMIO(0xc5104)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 97606c1be70d..bb1040275d4b 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -37,7 +37,7 @@
struct gmbus_pin {
const char *name;
- i915_reg_t reg;
+ enum i915_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */
@@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
else
size = ARRAY_SIZE(gmbus_pins);
- return pin < size &&
- i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
+ return pin < size && get_gmbus_pin(dev_priv, pin)->name;
}
/* Intel GPIO access functions */
@@ -293,7 +292,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
algo = &bus->bit_algo;
bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
- i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
+ 4 * get_gmbus_pin(dev_priv, pin)->gpio);
bus->adapter.algo_data = algo;
algo->setsda = set_data;
algo->setscl = set_clock;
@@ -775,11 +774,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ dev_priv->gpio_mmio_base = VLV_GPIO_BASE;
else if (!HAS_GMCH_DISPLAY(dev_priv))
- dev_priv->gpio_mmio_base =
- i915_mmio_reg_offset(PCH_GPIOA) -
- i915_mmio_reg_offset(GPIOA);
+ dev_priv->gpio_mmio_base = PCH_GPIO_BASE;
+ else
+ dev_priv->gpio_mmio_base = GPIO_OFFSET;
mutex_init(&dev_priv->gmbus_mutex);
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
--
2.17.1
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