[Intel-gfx] [PATCH] drm/i915: Flush the WCB following a WC write

[Matthew Auld]

On 6 July 2018 at 12:54, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> If we have just completed a WC write, we must ensure that the WCB (Write
> Combining Buffer) is flushed out to main memory before we can expect to
> see the results. This is especially important when mixing WC with GTT as
> the physical paths are different and cachelines are not naturally flushed.
>
> Testcase: igt/drv_selftests/live_coherency #gdg
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld at intel.com>