[Intel-gfx] [PATCH] drm/i915/selftests: Adjust y-tiling height for older machines

[Rodrigo Vivi]

On Fri, Jul 06, 2018 at 06:15:37PM +0100, Chris Wilson wrote:
> Older machines do not have the 128-byte tile width format for
> I915_TILING_Y and so we must adapt our reference swizzle.
> 
> Testcase: igt/drv_selftest/live_objects #gdg

The change below itself makes sense to me, but I'm trying to understand
where this came from....

Looking to https://intel-gfx-ci.01.org/tree/drm-tip/igt@drv_selftest@live_objects.html
is this related to issues on fi-gdg-551?

Or is this related to that APL bugzilla entry?

> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> index 6fe71865b710..8a35d2f70671 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
> @@ -171,7 +171,7 @@ static u64 tiled_offset(const struct tile *tile, u64 v)
>  		v += x;
>  	} else {
>  		const unsigned int ytile_span = 16;

could we also figure this value from somewhere else instead of
leaving it hardcoded for all platforms here?

> -		const unsigned int ytile_height = 32 * ytile_span;
> +		const unsigned int ytile_height = tile->height * ytile_span;
>  
>  		v += y * ytile_span;
>  		v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
> -- 
> 2.18.0
> 
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