[Intel-gfx] [PATCH v5 00/13] ICELAKE DSI DRIVER

[Madhav Chauhan]

>From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.

So, a new DSI driver has been added inside I915.

Given below patches are the part of new DSI driver which implements BSPEC
sequence till transcoder configuration. Rest of the patches published to GITHUB
and latest snapshot can be downloaded using:
#git clone https://github.com/madhavchauhan/Intel-DSI-Driver.git

v2: Addressed review comments from Jani N for Patches 1-6 and rebase for some
other few patches.
v3: Renamed intel_dsi_new.c to gen11_dsi.c as per discussion with Jani, Daniel,
    Ville. Also addressed review comments for couple of patches.
v4: Rename gen11_dsi.c to icl_dsi.c (Ville). No functional changes.
v5: Rebase on drm-tip after initial 7 patches got merged.

Madhav Chauhan (13):
  drm/i915/icl: Configure lane sequencing of combo phy transmitter
  drm/i915/icl: DSI vswing programming sequence
  drm/i915/icl: Enable DDI Buffer
  drm/i915/icl: Define T_INIT_MASTER registers
  drm/i915/icl: Program T_INIT_MASTER registers
  drm/i915/icl: Define data/clock lanes dphy timing registers
  drm/i915/icl: Program DSI clock and data lane timing params
  drm/i915/icl: Define TA_TIMING_PARAM registers
  drm/i915/icl: Program TA_TIMING_PARAM registers
  drm/i915/icl: Get DSI transcoder for a given port
  drm/i915/icl: Add macros for MMIO of DSI transcoder registers
  drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
  drm/i915/icl: Configure DSI transcoders

 drivers/gpu/drm/i915/i915_reg.h      | 112 ++++++++++++
 drivers/gpu/drm/i915/icl_dsi.c       | 324 +++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.h |   6 +-
 drivers/gpu/drm/i915/intel_dsi.h     |   7 +
 drivers/gpu/drm/i915/intel_dsi_vbt.c | 202 ++++++++++++++++------
 5 files changed, 593 insertions(+), 58 deletions(-)

-- 
2.7.4