[Intel-gfx] ✓ Fi.CI.BAT: success for ICELAKE DSI DRIVER (rev5)

[Patchwork]

== Series Details ==

Series: ICELAKE DSI DRIVER (rev5)
URL   : https://patchwork.freedesktop.org/series/44823/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4462 -> Patchwork_9603 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44823/revisions/5/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9603 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt at gem_exec_suspend@basic-s4-devices:
      fi-kbl-7500u:       PASS -> DMESG-WARN (fdo#105128, fdo#107139)

    igt at kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139


== Participating hosts (47 -> 40) ==

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-ctg-p8600 


== Build changes ==

    * Linux: CI_DRM_4462 -> Patchwork_9603

  CI_DRM_4462: d4e71d9d380fd82c93708cc29704a011dc9948ae @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4544: 764160f214cd916ddb79408b9f28ac0ad2df40e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9603: e04c020b54297b15e459bc86b3355202107738ea @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

e04c020b5429 drm/i915/icl: Configure DSI transcoders
0120accb0f10 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
2fa57a5edb01 drm/i915/icl: Add macros for MMIO of DSI transcoder registers
77e315ff7682 drm/i915/icl: Get DSI transcoder for a given port
4140659db9be drm/i915/icl: Program TA_TIMING_PARAM registers
d6b44b4626d5 drm/i915/icl: Define TA_TIMING_PARAM registers
647b5964795f drm/i915/icl: Program DSI clock and data lane timing params
5f50bd44df15 drm/i915/icl: Define data/clock lanes dphy timing registers
c76c29dcd686 drm/i915/icl: Program T_INIT_MASTER registers
e255c1a37c33 drm/i915/icl: Define T_INIT_MASTER registers
392c529052c6 drm/i915/icl: Enable DDI Buffer
c677ebaee69e drm/i915/icl: DSI vswing programming sequence
30f4f160de53 drm/i915/icl: Configure lane sequencing of combo phy transmitter

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9603/issues.html