[Intel-gfx] [PATCH 0/8] Remaining ICL display patches

[Paulo Zanoni]

These are the remaining patches from the series called "[PATCH 00/24]
More ICL display patches". Patches 1, 3 and 4 still need reviews.

Animesh Manna (1):
  drm/i915/icl: Update FIA supported lane count for hpd.

Paulo Zanoni (7):
  drm/i915/icl: compute the TBT PLL registers
  drm/i915/icl: implement icl_digital_port_connected()
  drm/i915/icl: store the port type for TC ports
  drm/i915/icl: implement the tc/legacy HPD {dis,}connect flow for DP
  drm/i915/icl: implement the legacy HPD {dis,}connect flow for HDMI
  drm/i915/icl: program MG_DP_MODE
  drm/i915/icl: toggle PHY clock gating around link training

 drivers/gpu/drm/i915/i915_reg.h       |  51 ++++++
 drivers/gpu/drm/i915/intel_ddi.c      |   5 +
 drivers/gpu/drm/i915/intel_display.h  |   7 +
 drivers/gpu/drm/i915/intel_dp.c       | 311 +++++++++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  22 ++-
 drivers/gpu/drm/i915/intel_drv.h      |   4 +
 drivers/gpu/drm/i915/intel_hdmi.c     |  11 +-
 7 files changed, 406 insertions(+), 5 deletions(-)

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2.14.4