[Intel-gfx] [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT

[Bloomfield, Jon]

> -----Original Message-----
> From: Chris Wilson <chris at chris-wilson.co.uk>
> Sent: Friday, July 13, 2018 1:06 AM
> To: Bloomfield, Jon <jon.bloomfield at intel.com>; Zhenyu Wang
> <zhenyuw at linux.intel.com>
> Cc: intel-gfx at lists.freedesktop.org; Zhenyu Wang
> <zhenyuw at linux.intel.com>; Joonas Lahtinen
> <joonas.lahtinen at linux.intel.com>; Matthew Auld
> <matthew.william.auld at gmail.com>
> Subject: Re: [PATCH 3/6] drm/i915/gtt: Disable read-only support under GVT
> 
> Quoting Zhenyu Wang (2018-07-13 03:03:10)
> > On 2018.07.12 20:36:03 +0000, Bloomfield, Jon wrote:
> > > > -----Original Message-----
> > > > From: Chris Wilson <chris at chris-wilson.co.uk>
> > > > Sent: Thursday, July 12, 2018 11:53 AM
> > > > To: intel-gfx at lists.freedesktop.org
> > > > Cc: Chris Wilson <chris at chris-wilson.co.uk>; Zhenyu Wang
> > > > <zhenyuw at linux.intel.com>; Bloomfield, Jon
> <jon.bloomfield at intel.com>;
> > > > Joonas Lahtinen <joonas.lahtinen at linux.intel.com>; Matthew Auld
> > > > <matthew.william.auld at gmail.com>
> > > > Subject: [PATCH 3/6] drm/i915/gtt: Disable read-only support under
> GVT
> > > >
> > > > GVT is not propagating the PTE bits, and is always setting the
> > > > read-write bit, thus breaking read-only support.
> > > >
> > > > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > > > Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> > > > Cc: Jon Bloomfield <jon.bloomfield at intel.com>
> > > > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> > > > Cc: Matthew Auld <matthew.william.auld at gmail.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++--
> > > >  1 file changed, 6 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > > index 6c0b438afe46..8e70a45b8a90 100644
> > > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > > > @@ -1662,8 +1662,12 @@ static struct i915_hw_ppgtt
> > > > *gen8_ppgtt_create(struct drm_i915_private *i915)
> > > >             1ULL << 48 :
> > > >             1ULL << 32;
> > > >
> > > > -   /* From bdw, there is support for read-only pages in the PPGTT */
> > > > -   ppgtt->vm.has_read_only = true;
> > > > +   /*
> > > > +    * From bdw, there is support for read-only pages in the PPGTT.
> > > > +    *
> > > > +    * XXX GVT is not setting honouring the PTE bits.
> > > > +    */
> > > > +   ppgtt->vm.has_read_only = !intel_vgpu_active(i915);
> > > >
> > > >     i915_address_space_init(&ppgtt->vm, i915);
> > > >
> > > > --
> > > > 2.18.0
> > >
> > > Is there a blocker that prevents gvt respecting this bit? I can't think of an
> obvious
> > > reason why it would be a bad thing to support.
> >
> > I don't think any blocker for gvt support, we can respect that bit when
> shadowing.
> > But we need capability check on host gvt when that support is ready.
> 
> Another cap bit required, so ack on both sides?
> -Chris
I see. Not as permanent disable, just more plumbing needed.
I'm happy then :-)
Reviewed-by: Jon Bloomfield <jon.bloomfield at intel.com>