[Intel-gfx] [PATCH v3 2/2] drm/i915: remove PCH_GMBUS defines
Lucas De Marchi
lucas.demarchi at intel.com
Fri Jul 13 15:42:12 UTC 2018
Use GMBUS* macros which computes the address using the gpio_mmio_base.
For that we just need access to dev_priv in a few places so this has
been added.
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
---
drivers/gpu/drm/i915/gvt/edid.c | 42 +++++++++++++++++------------
drivers/gpu/drm/i915/gvt/handlers.c | 8 +++---
drivers/gpu/drm/i915/i915_reg.h | 7 -----
3 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 4b98539025c5..3ffa814a634e 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -109,9 +109,11 @@ static inline int get_port_from_gmbus0(u32 gmbus0)
static void reset_gmbus_controller(struct intel_vgpu *vgpu)
{
- vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+ vgpu_vreg_t(vgpu, GMBUS2) = GMBUS_HW_RDY;
if (!vgpu->display.i2c_edid.edid_available)
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER;
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
}
@@ -141,22 +143,23 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
vgpu->display.i2c_edid.state = I2C_GMBUS;
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
!intel_vgpu_port_is_dp(vgpu, port)) {
vgpu->display.i2c_edid.port = port;
vgpu->display.i2c_edid.edid_available = true;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_SATOER;
} else
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER;
return 0;
}
static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
u32 slave_addr;
u32 wvalue = *(u32 *)p_data;
@@ -177,8 +180,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* 2) HW_RDY bit asserted
*/
if (wvalue & GMBUS_SW_CLR_INT) {
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_INT;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY;
}
/* For virtualization, we suppose that HW is always ready,
@@ -226,7 +229,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* visible in gmbus interface)
*/
i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE;
}
break;
case NIDX_NS_W:
@@ -238,7 +241,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* START (-->INDEX) -->DATA
*/
i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_ACTIVE;
break;
default:
gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
@@ -265,6 +268,7 @@ static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
int i;
unsigned char byte_data;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
@@ -274,7 +278,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
u32 reg_data = 0;
/* Data can only be recevied if previous settings correct */
- if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
+ if (vgpu_vreg_t(vgpu, GMBUS1) & GMBUS_SLAVE_READ) {
if (byte_left <= 0) {
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
return 0;
@@ -350,12 +354,14 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
- if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+ if (offset == i915_mmio_reg_offset(GMBUS2))
return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+ else if (offset == i915_mmio_reg_offset(GMBUS3))
return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
@@ -375,16 +381,18 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
- if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
+ if (offset == i915_mmio_reg_offset(GMBUS0))
return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
+ else if (offset == i915_mmio_reg_offset(GMBUS1))
return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+ else if (offset == i915_mmio_reg_offset(GMBUS2))
return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+ else if (offset == i915_mmio_reg_offset(GMBUS3))
return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ecff866bbbf1..185e6c3002e5 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2116,8 +2116,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0x48268), D_ALL);
- MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
- gmbus_mmio_write);
+ MMIO_F(GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
+ gmbus_mmio_write);
MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
@@ -2507,8 +2507,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0xe6704), D_ALL);
MMIO_D(_MMIO(0xe6800), D_ALL);
MMIO_D(_MMIO(0xe6804), D_ALL);
- MMIO_D(PCH_GMBUS4, D_ALL);
- MMIO_D(PCH_GMBUS5, D_ALL);
+ MMIO_D(GMBUS4, D_ALL);
+ MMIO_D(GMBUS5, D_ALL);
MMIO_D(_MMIO(0x902c), D_ALL);
MMIO_D(_MMIO(0xec008), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e3ba9898f4e..e01e98ff8c30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7664,13 +7664,6 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GMBUS0 _MMIO(0xc5100)
-#define PCH_GMBUS1 _MMIO(0xc5104)
-#define PCH_GMBUS2 _MMIO(0xc5108)
-#define PCH_GMBUS3 _MMIO(0xc510c)
-#define PCH_GMBUS4 _MMIO(0xc5110)
-#define PCH_GMBUS5 _MMIO(0xc5120)
-
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
--
2.17.1
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