[Intel-gfx] [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping

Chris Wilson chris at chris-wilson.co.uk
Thu Jul 19 19:01:12 UTC 2018


Quoting Ville Syrjala (2018-07-19 19:22:12)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The display engine stride limits are getting in our way. On SKL+
> we are limited to 8k pixels, which is easily exceeded with three
> 4k displays. To overcome this limitation we can remap the pages
> in the GTT to provide the display engine with a view of memory
> with a smaller stride.
> 
> The code is mostly already there as We already play tricks with
> the plane surface address and x/y offsets.
> 
> A few caveats apply:
> * linear buffers need the fb stride to be page aligned, as
>   otherwise the remapped lines wouldn't start at the same
>   spot
> * compressed buffers can't be remapped due to the new
>   ccs hash mode causing the virtual address of the pages
>   to affect the interpretation of the compressed data. IIRC
>   the old hash was limited to the low 12 bits so if we were
>   using that mode we could remap. As it stands we just refuse
>   to remapp with compressed fbs.
> * no remapping gen2/3 as we'd need a fence for the remapped
>   vma, which we currently don't have

But... you just forbade us getting a fence, there's nothing that
actually would stop the fence register assignment from working?
-Chris


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