[Intel-gfx] [PATCH] drm/i915: Fix gen-2 check for 128B tiling

[Dhinakaran Pandiyan]

On Sat, 2018-07-21 at 10:11 +0100, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-07-21 10:06:07)
> > 
> > intel_tile_width_bytes() returns 128B for gen-2 y-tiled buffers
> > while at
> > the same time HAS_128_BYTE_Y_TILING() returns false for gen-2. I am
> > assuming intel_tile_width_bytes() does the right thing.
> > 
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> It's rather that gen2 only has 128B tiling. Note that it only makes
> any
> difference for intel_tile_width_bytes()..

Okay, the macro is a bit misleading. Do you have any suggestions to
clarify it or would you prefer I leave it as it is?


> -Chris