[Intel-gfx] [PATCH] drm/i915/psr: Limit psr2 to skl+

[vathsala nagaraju]

From: Vathsala Nagaraju <vathsala.nagaraju at intel.com>

PSR2 is supported from skl+.
So Limiting it to skl+.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 4bd5768..cbbdfd2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -387,7 +387,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	I915_WRITE(EDP_PSR_CTL, val);
 }
 
-static void hsw_activate_psr2(struct intel_dp *intel_dp)
+static void skl_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
@@ -516,7 +516,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	}
 
 	crtc_state->has_psr = true;
-	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
+	if (INTEL_GEN(dev_priv) >= 9)
+		crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
+							       crtc_state);
 	DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");
 }
 
@@ -534,7 +536,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 
 	/* psr1 and psr2 are mutually exclusive.*/
 	if (dev_priv->psr.psr2_enabled)
-		hsw_activate_psr2(intel_dp);
+		skl_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
 
-- 
1.9.1