[Intel-gfx] [PATCH v6 3/6] drm/i915/guc: Move the pin bias value from GuC to GGTT

[Chris Wilson]

Quoting Jakub Bartmiński (2018-07-27 09:53:47)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index d0acef299b9c..8ac5214b3648 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2917,6 +2917,14 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>         struct drm_mm_node *entry;
>         int ret;
>  
> +       /*
> +        * GuC requires the ring to be placed in Non-WOPCM memory. If GuC is not
> +        * present or not in use we still need a small bias as ring wraparound
> +        * at offset 0 sometimes hangs. No idea why.
> +        */
> +       ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
> +                              intel_guc_wopcm_region_size(&dev_priv->guc));

Hmm, it feels like this should fit in with ggtt_init_hw, but the current
setup makes that impossible.

intel_guc_wopcm_region_size() is a peculiar path to access
dev_priv->wopcm.

Do we not want something like intel_wopcm_lower_reserved_size()?

> +/**
> + * intel_guc_wopcm_region_size() - Get the size of the GuC region of WOPCM.
> + * @guc: intel_guc structure.
> + *
> + * Returns:
> + * 0 if GuC is not present or not in use.
> + * Otherwise, the GuC WOPCM size.
> + */
> +u32 intel_guc_wopcm_region_size(struct intel_guc *guc)
> +{
> +       struct intel_wopcm *wopcm = &guc_to_i915(guc)->wopcm;
> +
> +       /* WOPCM must have already been partitioned */
> +       GEM_BUG_ON(!wopcm->size);

Unrelated bug-on, since what you want is a statement that
intel_wopcm_init() was called and that doesn't provide it.
-Chris