[Intel-gfx] [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions

[José Roberto de Souza]

It is not used anymore after 'drm/i915/cnl+: Reload CSR firmware when
coming back from low power state'.

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         |  2 +-
 drivers/gpu/drm/i915/intel_drv.h        |  2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ++++++++-----------
 3 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a42f0dfe19da..3aefaa6c9483 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2698,7 +2698,7 @@ static int intel_runtime_resume(struct device *kdev)
 
 	if (IS_GEN9_LP(dev_priv)) {
 		bxt_disable_dc9(dev_priv);
-		bxt_display_core_init(dev_priv, true);
+		bxt_display_core_init(dev_priv);
 		if (dev_priv->csr.dmc_payload) {
 			intel_csr_load_program(dev_priv);
 			if (dev_priv->csr.allowed_dc_mask &
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 99a5f5be5b82..c96f3b7b3eda 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1950,7 +1950,7 @@ void intel_power_domains_fini(struct drm_i915_private *);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
-void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void bxt_display_core_init(struct drm_i915_private *dev_priv);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 const char *
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8fdcffe023fe..d435476a6003 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3048,8 +3048,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(MBUS_ABOX_CTL, val);
 }
 
-static void skl_display_core_init(struct drm_i915_private *dev_priv,
-				   bool resume)
+static void skl_display_core_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
@@ -3107,8 +3106,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 	usleep_range(10, 30);		/* 10 us delay per Bspec */
 }
 
-void bxt_display_core_init(struct drm_i915_private *dev_priv,
-			   bool resume)
+void bxt_display_core_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
@@ -3233,7 +3231,7 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
 	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
 }
 
-static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+static void cnl_display_core_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
@@ -3313,8 +3311,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
 	I915_WRITE(CHICKEN_MISC_2, val);
 }
 
-static void icl_display_core_init(struct drm_i915_private *dev_priv,
-				  bool resume)
+static void icl_display_core_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	struct i915_power_well *well;
@@ -3533,13 +3530,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
 	power_domains->initializing = true;
 
 	if (IS_ICELAKE(dev_priv)) {
-		icl_display_core_init(dev_priv, resume);
+		icl_display_core_init(dev_priv);
 	} else if (IS_CANNONLAKE(dev_priv)) {
-		cnl_display_core_init(dev_priv, resume);
+		cnl_display_core_init(dev_priv);
 	} else if (IS_GEN9_BC(dev_priv)) {
-		skl_display_core_init(dev_priv, resume);
+		skl_display_core_init(dev_priv);
 	} else if (IS_GEN9_LP(dev_priv)) {
-		bxt_display_core_init(dev_priv, resume);
+		bxt_display_core_init(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
 		mutex_lock(&power_domains->lock);
 		chv_phy_control_init(dev_priv);
-- 
2.18.0