[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Display Stream Compression on eDP/DP (rev2)

Patchwork patchwork at emeril.freedesktop.org
Tue Jul 31 17:45:50 UTC 2018 

== Series Details ==

Series: Enable Display Stream Compression on eDP/DP (rev2)
URL   : https://patchwork.freedesktop.org/series/47461/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
27c39427ec85 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
5c8ad85804c4 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
-:62: CHECK:SPACING: No space is necessary after a cast
#62: FILE: drivers/gpu/drm/i915/intel_dp.c:3898:
+			      (int) sizeof(intel_dp->dsc_dpcd),

total: 0 errors, 0 warnings, 1 checks, 63 lines checked
0081fe19d05d drm/dp: DRM DP helper/macros to get DP sink DSC parameters
08e091309edb drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#24: 
* rename it as SMALL_JOINER since we are not enabling big joiner yet (Anusha)

-:115: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#115: FILE: drivers/gpu/drm/i915/intel_dp.c:4150:
+	 * fractional part is 0 */

total: 0 errors, 2 warnings, 0 checks, 131 lines checked
aead51650cbe drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
518d81d5eff2 drm/dp: Define payload size for DP SDP PPS packet
4e91c7ad5834 drm/dsc: Define Display Stream Compression PPS infoframe
-:21: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#21: 
new file mode 100644

-:26: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#26: FILE: include/drm/drm_dsc.h:1:
+/*

total: 0 errors, 2 warnings, 0 checks, 365 lines checked
dfce08e3cd4a drm/dsc: Define VESA Display Stream Compression Capabilities
d93be48c680f drm/dsc: Define Rate Control values that do not change over configurations
411f986ec2b2 drm/dsc: Add helpers for DSC picture parameter set infoframes
-:19: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#19: 
* Add reference to added kernel-docs in Documentation/gpu/drm-kms-helpers.rst

-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#69: 
new file mode 100644

-:74: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#74: FILE: drivers/gpu/drm/drm_dsc.c:1:
+/*

-:210: WARNING:LONG_LINE: line over 100 characters
#210: FILE: drivers/gpu/drm/drm_dsc.c:137:
+	pps_sdp->pps_payload.scale_increment_interval = cpu_to_be16(dsc_cfg->scale_increment_interval);

-:213: WARNING:LONG_LINE: line over 100 characters
#213: FILE: drivers/gpu/drm/drm_dsc.c:140:
+	pps_sdp->pps_payload.scale_decrement_interval_high = (u8)((dsc_cfg->scale_decrement_interval &

-:214: WARNING:LONG_LINE: line over 100 characters
#214: FILE: drivers/gpu/drm/drm_dsc.c:141:
+								   DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>

-:276: WARNING:LONG_LINE: line over 100 characters
#276: FILE: drivers/gpu/drm/drm_dsc.c:203:
+		pps_sdp->pps_payload.rc_range_parameters[i] = cpu_to_be16(pps_sdp->pps_payload.rc_range_parameters[i]);

total: 0 errors, 7 warnings, 0 checks, 285 lines checked
aa96679ec57e drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
797cfde71a78 drm/i915/dp: Compute DSC pipe config in atomic check
-:122: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#122: FILE: drivers/gpu/drm/i915/intel_dp.c:1909:
+			bpp = 3*bpc;
 			       ^

-:183: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#183: FILE: drivers/gpu/drm/i915/intel_dp.c:2016:
+	} else {
+

-:205: CHECK:BRACES: braces {} should be used on all arms of this statement
#205: FILE: drivers/gpu/drm/i915/intel_dp.c:2038:
+		if (pipe_config->dsc_params.slice_count > 1)
[...]
+		else {
[...]

-:207: CHECK:BRACES: Unbalanced braces around else statement
#207: FILE: drivers/gpu/drm/i915/intel_dp.c:2040:
+		else {

total: 0 errors, 0 warnings, 4 checks, 256 lines checked
ea64a4506689 drm/i915/dp: Do not enable PSR2 if DSC is enabled
296fd9b47516 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
e1de0bb838ae drm/i915/dsc: Define & Compute VESA DSC params
-:82: WARNING:MISSING_SPACE: break quoted strings at a space character
#82: FILE: drivers/gpu/drm/i915/intel_dp.c:2047:
+		DRM_ERROR("Cannot compute valid DSC parameters for Input Bpp = %d"
+			  "Compressed BPP = %d\n",

-:100: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#100: FILE: drivers/gpu/drm/i915/intel_drv.h:1756:
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+					struct intel_crtc_state *pipe_config);

-:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#106: 
new file mode 100644

-:111: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#111: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1:
+/*

-:410: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#410: FILE: drivers/gpu/drm/i915/intel_vdsc.c:300:
+}
+};

-:449: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#449: FILE: drivers/gpu/drm/i915/intel_vdsc.c:339:
+int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
+					struct intel_crtc_state *pipe_config)

-:460: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#460: FILE: drivers/gpu/drm/i915/intel_vdsc.c:350:
+	vdsc_cfg->slice_width = DIV_ROUND_UP(

-:476: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#476: FILE: drivers/gpu/drm/i915/intel_vdsc.c:366:
+	vdsc_cfg->dsc_version_major = (

-:480: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#480: FILE: drivers/gpu/drm/i915/intel_vdsc.c:370:
+	vdsc_cfg->dsc_version_minor = min(DSC_SUPPORTED_VERSION_MIN,
+			(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &

-:483: CHECK:OPEN_ENDED_LINE: Lines should not end with a '['
#483: FILE: drivers/gpu/drm/i915/intel_vdsc.c:373:
+	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[

-:500: CHECK:OPEN_ENDED_LINE: Lines should not end with a '['
#500: FILE: drivers/gpu/drm/i915/intel_vdsc.c:390:
+			intel_dp->dsc_dpcd[

-:559: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#559: FILE: drivers/gpu/drm/i915/intel_vdsc.c:449:
+	if (vdsc_cfg->bits_per_component == 8 ||
+					vdsc_cfg->bits_per_component == 10)

total: 0 errors, 3 warnings, 9 checks, 508 lines checked
019eec0259af drm/i915/dsc: Compute Rate Control parameters for DSC
-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/intel_vdsc.c:352:
+	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
+						DP_DSC_RC_PIXELS_PER_GROUP);

-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/intel_vdsc.c:370:
+	while ((num_extra_mux_bits > 0) &&
+		((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))

-:104: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#104: FILE: drivers/gpu/drm/i915/intel_vdsc.c:401:
+		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP(

-:120: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#120: FILE: drivers/gpu/drm/i915/intel_vdsc.c:417:
+	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(

-:134: CHECK:SPACING: space preferred before that '*' (ctx:VxE)
#134: FILE: drivers/gpu/drm/i915/intel_vdsc.c:431:
+				vdsc_cfg->slice_bpg_offset)*
 				                           ^

-:166: CHECK:LINE_SPACING: Please don't use multiple blank lines
#166: FILE: drivers/gpu/drm/i915/intel_vdsc.c:463:
+
+

total: 0 errors, 0 warnings, 6 checks, 140 lines checked
aa794586ed2a drm/i915/dp: Enable/Disable DSC in DP Sink
363456f7ee95 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
-:27: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#27: FILE: drivers/gpu/drm/i915/i915_drv.h:3436:
+extern void intel_dsc_enable(struct intel_encoder *encoder,

-:315: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#315: FILE: drivers/gpu/drm/i915/intel_vdsc.c:847:
+		rc_buf_thresh_dword[i/4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 		                     ^

-:316: CHECK:SPACING: spaces preferred around that '%' (ctx:VxV)
#316: FILE: drivers/gpu/drm/i915/intel_vdsc.c:848:
+						  BITS_PER_BYTE * (i%4));
 						                    ^

-:318: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#318: FILE: drivers/gpu/drm/i915/intel_vdsc.c:850:
+			 rc_buf_thresh_dword[i/4]);
 			                      ^

-:359: WARNING:LONG_LINE: line over 100 characters
#359: FILE: drivers/gpu/drm/i915/intel_vdsc.c:891:
+		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<

-:359: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#359: FILE: drivers/gpu/drm/i915/intel_vdsc.c:891:
+		rc_range_params_dword[i/2] |= (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 		                       ^

-:364: CHECK:SPACING: spaces preferred around that '%' (ctx:VxV)
#364: FILE: drivers/gpu/drm/i915/intel_vdsc.c:896:
+						      RC_MIN_QP_SHIFT)) << 16 * (i%2));
 						                                  ^

-:366: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#366: FILE: drivers/gpu/drm/i915/intel_vdsc.c:898:
+			 rc_range_params_dword[i/2]);
 			                        ^

-:466: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#466: FILE: drivers/gpu/drm/i915/intel_vdsc.c:998:
+{
+

-:473: WARNING:RETURN_VOID: void function return statements are not generally useful
#473: FILE: drivers/gpu/drm/i915/intel_vdsc.c:1005:
+	return;
+}

total: 0 errors, 2 warnings, 8 checks, 440 lines checked
2fb6aeab6aeb drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs
3e5086ab7ce0 drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes
74c50a243b19 drm/i915/icl: Add Display Stream Splitter control registers
93dd5a51c49a drm/i915/dp: Configure Display stream splitter registers during DSC enable
c518575b081f drm/i915/dp: Disable DSC in source by disabling DSS CTL bits

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