[Intel-gfx] ✗ Fi.CI.BAT: failure for Display Stream Compression enabling on eDP/DP

[Patchwork]

== Series Details ==

Series: Display Stream Compression enabling on eDP/DP
URL   : https://patchwork.freedesktop.org/series/47514/
State : failure

== Summary ==

Applying: drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT
Applying: drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init
Applying: drm/dp: DRM DP helper/macros to get DP sink DSC parameters
Applying: drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC
Applying: drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported
Applying: drm/dp: Define payload size for DP SDP PPS packet
Applying: drm/dsc: Define Display Stream Compression PPS infoframe
Applying: drm/dsc: Define VESA Display Stream Compression Capabilities
Applying: drm/dsc: Define Rate Control values that do not change over configurations
Applying: drm/dsc: Add helpers for DSC picture parameter set infoframes
Applying: drm/i915/dp: Add DSC params and DSC config to intel_crtc_state
Applying: drm/i915/dp: Compute DSC pipe config in atomic check
Applying: drm/i915/dp: Do not enable PSR2 if DSC is enabled
Applying: drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
Applying: drm/i915/dsc: Define & Compute VESA DSC params
Applying: drm/i915/dsc: Compute Rate Control parameters for DSC
Applying: drm/i915/dp: Enable/Disable DSC in DP Sink
Applying: drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_display.c).
error: could not build fake ancestor
Patch failed at 0018 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".