[Intel-gfx] [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT

[Srivatsa, Anusha]

>-----Original Message-----
>From: Navare, Manasi D
>Sent: Tuesday, July 31, 2018 2:07 PM
>To: intel-gfx at lists.freedesktop.org
>Cc: Navare, Manasi D <manasi.d.navare at intel.com>; dri-
>devel at lists.freedesktop.org; Jani Nikula <jani.nikula at linux.intel.com>; Ville
>Syrjala <ville.syrjala at linux.intel.com>; Srivatsa, Anusha
><anusha.srivatsa at intel.com>; Singh, Gaurav K <gaurav.k.singh at intel.com>
>Subject: [PATCH v2 01/23] drm/dp: Add DP DSC DPCD receiver capability size
>define and missing SHIFT
>
>This patch defines the DP DSC receiver capability size that gives total number of
>DP DSC DPCD registers.
>This also adds a missing #defines for DP DSC support missed in the commit id
>(ab6a46ea6842ce "Add DPCD definitions for DP 1.4 DSC feature")
>
>v3:
>* MIN_SLICE_WIDTH = 2560 (Anusha)
>* Define DP_DSC_SLICE_WIDTH_MULTIPLIER = 320
>v2:
>* Add SHIFT define and DECOMPRESSION_EN define misse din prev patch
							^^^ "missed in previous"							
>Cc: dri-devel at lists.freedesktop.org
>Cc: Jani Nikula <jani.nikula at linux.intel.com>
>Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
>Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
>Cc: Gaurav K Singh <gaurav.k.singh at intel.com>
>Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
Other than the typo, the patch looks good.
Checked with Spec.

Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
>---
> include/drm/drm_dp_helper.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
>diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index
>05cc31b..eb0d86c 100644
>--- a/include/drm/drm_dp_helper.h
>+++ b/include/drm/drm_dp_helper.h
>@@ -230,6 +230,8 @@
> #define DP_DSC_MAX_BITS_PER_PIXEL_LOW       0x067   /* eDP 1.4 */
>
> #define DP_DSC_MAX_BITS_PER_PIXEL_HI        0x068   /* eDP 1.4 */
>+# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK  (0x3 << 0) # define
>+DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
>
> #define DP_DSC_DEC_COLOR_FORMAT_CAP         0x069
> # define DP_DSC_RGB                         (1 << 0)
>@@ -278,6 +280,8 @@
> # define DP_DSC_THROUGHPUT_MODE_1_1000      (14 << 4)
>
> #define DP_DSC_MAX_SLICE_WIDTH              0x06C
>+#define DP_DSC_MIN_SLICE_WIDTH_VALUE        2560
>+#define DP_DSC_SLICE_WIDTH_MULTIPLIER       320
>
> #define DP_DSC_SLICE_CAP_2                  0x06D
> # define DP_DSC_16_PER_DP_DSC_SINK          (1 << 0)
>@@ -476,6 +480,7 @@
> # define DP_AUX_FRAME_SYNC_VALID	    (1 << 0)
>
> #define DP_DSC_ENABLE                       0x160   /* DP 1.4 */
>+# define DP_DECOMPRESSION_EN                (1 << 0)
>
> #define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
> # define DP_PSR_ENABLE			    (1 << 0)
>@@ -962,6 +967,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8
>link_status[DP_LINK_STATUS_SI
>
> #define DP_BRANCH_OUI_HEADER_SIZE	0xc
> #define DP_RECEIVER_CAP_SIZE		0xf
>+#define DP_DSC_RECEIVER_CAP_SIZE        0xf
> #define EDP_PSR_RECEIVER_CAP_SIZE	2
> #define EDP_DISPLAY_CTL_CAP_SIZE	3
>
>--
>2.7.4