[Intel-gfx] [PATCH] drm/i915/perf: fix gen11 engine class shift

[Chris Wilson]

Quoting Michel Thierry (2018-06-04 19:17:24)
> Use the correct engine class shift value while storing the ctx hw id.
> Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
> ctx_id read with GuC & ICL").
> 
> Apologies for not spotting this in the original review, the
> specific_ctx_id_mask is correct, only the specific_ctx_id had this
> problem.
> 
> Signed-off-by: Michel Thierry <michel.thierry at intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_perf.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index a6c8d61add0c..c15c7b0fb482 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1291,7 +1291,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
>                 i915->perf.oa.specific_ctx_id =
>                         stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
>                         engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
> -                       engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
> +                       engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);

Hmm, isn't this upper_32_bits(ce->lrc_desc) ?
-Chris