[Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI

Srivatsa, Anusha anusha.srivatsa at intel.com
Tue Jun 5 00:12:57 UTC 2018



>-----Original Message-----
>From: Navare, Manasi D
>Sent: Wednesday, May 23, 2018 9:47 AM
>To: Srivatsa, Anusha <anusha.srivatsa at intel.com>
>Cc: intel-gfx at lists.freedesktop.org; Zanoni, Paulo R <paulo.r.zanoni at intel.com>
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers and
>bitfields for MG PHY DDI
>
>On Tue, May 22, 2018 at 11:04:57PM -0700, Srivatsa, Anusha wrote:
>>
>>
>> >-----Original Message-----
>> >From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On
>> >Behalf Of Manasi Navare
>> >Sent: Tuesday, May 15, 2018 5:53 PM
>> >To: intel-gfx at lists.freedesktop.org
>> >Cc: Zanoni, Paulo R <paulo.r.zanoni at intel.com>
>> >Subject: [Intel-gfx] [PATCH] drm/i915/icl: Add remaining registers
>> >and bitfields for MG PHY DDI
>> >
>> >This patch adds the remaining register definitions and bit fields
>> >required for MG PHy DDI buffer initializations and voltage swing
>> >programming for MG PHy DDI ports.
>> >
>> >While at it this patch also fixes the naming for previously defined
>> >MG PHY registers in original commit id (c92f47b5ec977a "drm/i915/icl:
>> >Add register defs for voltage swing sequences for MG PHY DDI").
>> >Since the MG PHY registers are first defined in ICL platform, there
>> >is no need for _ICL prefix.
>> >
>> >Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
>> >Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
>> >Cc: James Ausmus <james.ausmus at intel.com>
>> >---
>> > drivers/gpu/drm/i915/i915_reg.h | 243
>> >+++++++++++++++++++++++----------------
>> >-
>> > 1 file changed, 142 insertions(+), 101 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> >b/drivers/gpu/drm/i915/i915_reg.h index f11bb21..a93b796 100644
>> >--- a/drivers/gpu/drm/i915/i915_reg.h
>> >+++ b/drivers/gpu/drm/i915/i915_reg.h
>> >@@ -1827,121 +1827,162 @@ enum i915_power_well_id {
>> > #define   N_SCALAR(x)			((x) << 24)
>> > #define   N_SCALAR_MASK			(0x7F << 24)
>> >
>> >-#define _ICL_MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
>> >+#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \
>> > 	_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) -
>> > (ln0p1)))
>> >
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
>> >-#define ICL_PORT_MG_TX1_LINK_PARAMS(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>> >-
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
>> >-#define _ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
>> >-#define ICL_PORT_MG_TX2_LINK_PARAMS(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>> >-
>> >_ICL_MG_TX_LINK_PARAMS_TX2LN1_PORT1)
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT1		0x16812C
>> >+#define MG_TX_LINK_PARAMS_TX1LN1_PORT1		0x16852C
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT2		0x16912C
>> >+#define MG_TX_LINK_PARAMS_TX1LN1_PORT2		0x16952C
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT3		0x16A12C
>> >+#define MG_TX_LINK_PARAMS_TX1LN1_PORT3		0x16A52C
>> >+#define MG_TX_LINK_PARAMS_TX1LN0_PORT4		0x16B12C
>> >+#define _MG_TX_LINK_PARAMS_TX1LN1_PORT4		0x16B52C
>> >+#define MG_TX1_LINK_PARAMS(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \
>> >+				 MG_TX_LINK_PARAMS_TX1LN0_PORT2, \
>> >+				 MG_TX_LINK_PARAMS_TX1LN1_PORT1)
>> >+
>> >+#define MG_TX_LINK_PARAMS_TX2LN0_PORT1		0x1680AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN1_PORT1		0x1684AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN0_PORT2		0x1690AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN1_PORT2		0x1694AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN0_PORT3		0x16A0AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN1_PORT3		0x16A4AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN0_PORT4		0x16B0AC
>> >+#define MG_TX_LINK_PARAMS_TX2LN1_PORT4		0x16B4AC
>> >+#define MG_TX2_LINK_PARAMS(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \
>> >+				 MG_TX_LINK_PARAMS_TX2LN0_PORT2, \
>> >+				 MG_TX_LINK_PARAMS_TX2LN1_PORT1)
>> > #define CRI_USE_FS32			(1 << 5)
>>
>> Not a complete review of the patch, but noticed that most bitfields here are
>missing.
>> Apart from CRI_USE_FS2, there are others like CRI_REVERSEDEEMPH_EN etc...
>are they skipped on purpose?
>>
>
>Yes actually only the register bitfields that re required for the DDI Buffer
>initializations and voltage swing programming are defined here.
>
>Manasi
>
>> Anusha
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1
>	0x16814C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1
>	0x16854C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2
>	0x16914C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT2
>	0x16954C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT3
>	0x16A14C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT3
>	0x16A54C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT4
>	0x16B14C
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT4
>	0x16B54C
>> >-#define ICL_PORT_MG_TX1_PISO_READLOAD(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
>> >-
>> >_ICL_MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
>> >-
>> >_ICL_MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>> >-
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1
>	0x1680CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1
>	0x1684CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2
>	0x1690CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT2
>	0x1694CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT3
>	0x16A0CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT3
>	0x16A4CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT4
>	0x16B0CC
>> >-#define _ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT4
>	0x16B4CC
>> >-#define ICL_PORT_MG_TX2_PISO_READLOAD(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
>> >-
>> >_ICL_MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
>> >-
>> >_ICL_MG_TX_PISO_READLOAD_TX2LN1_PORT1)
>> >+#define MG_TX_PISO_READLOAD_TX1LN0_PORT1		0x16814C
>> >+#define MG_TX_PISO_READLOAD_TX1LN1_PORT1		0x16854C
>> >+#define MG_TX_PISO_READLOAD_TX1LN0_PORT2		0x16914C
>> >+#define MG_TX_PISO_READLOAD_TX1LN1_PORT2		0x16954C
>> >+#define MG_TX_PISO_READLOAD_TX1LN0_PORT3		0x16A14C
>> >+#define MG_TX_PISO_READLOAD_TX1LN1_PORT3		0x16A54C
>> >+#define MG_TX_PISO_READLOAD_TX1LN0_PORT4		0x16B14C
>> >+#define MG_TX_PISO_READLOAD_TX1LN1_PORT4		0x16B54C
>> >+#define MG_TX1_PISO_READLOAD(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \
>> >+				 MG_TX_PISO_READLOAD_TX1LN0_PORT2, \
>> >+				 MG_TX_PISO_READLOAD_TX1LN1_PORT1)
>> >+
>> >+#define MG_TX_PISO_READLOAD_TX2LN0_PORT1		0x1680CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN1_PORT1		0x1684CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN0_PORT2		0x1690CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN1_PORT2		0x1694CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN0_PORT3		0x16A0CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN1_PORT3		0x16A4CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN0_PORT4		0x16B0CC
>> >+#define MG_TX_PISO_READLOAD_TX2LN1_PORT4		0x16B4CC
>> >+#define MG_TX2_PISO_READLOAD(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \
>> >+				 MG_TX_PISO_READLOAD_TX2LN0_PORT2, \
>> >+				 MG_TX_PISO_READLOAD_TX2LN1_PORT1)
>> > #define CRI_CALCINIT					(1 << 1)
>> >
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
>> >-#define _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
>> >-#define ICL_PORT_MG_TX1_SWINGCTRL(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_SWINGCTRL_TX1LN0_PORT1, \
>> >-				      _ICL_MG_TX_SWINGCTRL_TX1LN0_PORT2, \
>> >-				      _ICL_MG_TX_SWINGCTRL_TX1LN1_PORT1)
>> >-
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
>> >-#define _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
>> >-#define ICL_PORT_MG_TX2_SWINGCTRL(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_SWINGCTRL_TX2LN0_PORT1, \
>> >-				      _ICL_MG_TX_SWINGCTRL_TX2LN0_PORT2, \
>> >-				      _ICL_MG_TX_SWINGCTRL_TX2LN1_PORT1)
>> >+#define MG_TX_SWINGCTRL_TX1LN0_PORT1		0x168148
>> >+#define MG_TX_SWINGCTRL_TX1LN1_PORT1		0x168548
>> >+#define MG_TX_SWINGCTRL_TX1LN0_PORT2		0x169148
>> >+#define MG_TX_SWINGCTRL_TX1LN1_PORT2		0x169548
>> >+#define MG_TX_SWINGCTRL_TX1LN0_PORT3		0x16A148
>> >+#define MG_TX_SWINGCTRL_TX1LN1_PORT3		0x16A548
>> >+#define MG_TX_SWINGCTRL_TX1LN0_PORT4		0x16B148
>> >+#define MG_TX_SWINGCTRL_TX1LN1_PORT4		0x16B548
>> >+#define MG_TX1_SWINGCTRL(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \
>> >+				 MG_TX_SWINGCTRL_TX1LN0_PORT2, \
>> >+				 MG_TX_SWINGCTRL_TX1LN1_PORT1)
>> >+
>> >+#define MG_TX_SWINGCTRL_TX2LN0_PORT1		0x1680C8
>> >+#define MG_TX_SWINGCTRL_TX2LN1_PORT1		0x1684C8
>> >+#define MG_TX_SWINGCTRL_TX2LN0_PORT2		0x1690C8
>> >+#define MG_TX_SWINGCTRL_TX2LN1_PORT2		0x1694C8
>> >+#define MG_TX_SWINGCTRL_TX2LN0_PORT3		0x16A0C8
>> >+#define MG_TX_SWINGCTRL_TX2LN1_PORT3		0x16A4C8
>> >+#define MG_TX_SWINGCTRL_TX2LN0_PORT4		0x16B0C8
>> >+#define MG_TX_SWINGCTRL_TX2LN1_PORT4		0x16B4C8
>> >+#define MG_TX2_SWINGCTRL(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \
>> >+				 MG_TX_SWINGCTRL_TX2LN0_PORT2, \
>> >+				 MG_TX_SWINGCTRL_TX2LN1_PORT1)
>> > #define CRI_TXDEEMPH_OVERRIDE_17_12(x)			((x) << 0)
>> > #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK		(0x3F << 0)
>> >
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT1
>> >	0x168144
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1
>> >	0x168544
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2
>> >	0x169144
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT2
>> >	0x169544
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT3
>> >	0x16A144
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT3
>> >	0x16A544
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN0_PORT4
>> >	0x16B144
>> >-#define _ICL_MG_TX_DRVCTRL_TX1LN1_PORT4
>> >	0x16B544
>> >-#define ICL_PORT_MG_TX1_DRVCTRL(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_DRVCTRL_TX1LN0_PORT1, \
>> >-				      _ICL_MG_TX_DRVCTRL_TX1LN0_PORT2, \
>> >-				      _ICL_MG_TX_DRVCTRL_TX1LN1_PORT1)
>> >-
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT1
>> >	0x1680C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1
>> >	0x1684C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2
>> >	0x1690C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT2
>> >	0x1694C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT3
>> >	0x16A0C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT3
>> >	0x16A4C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN0_PORT4
>> >	0x16B0C4
>> >-#define _ICL_MG_TX_DRVCTRL_TX2LN1_PORT4
>> >	0x16B4C4
>> >-#define ICL_PORT_MG_TX2_DRVCTRL(port, ln) \
>> >-	_ICL_MG_PHY_PORT_LN(port, ln,
>> >_ICL_MG_TX_DRVCTRL_TX2LN0_PORT1, \
>> >-				      _ICL_MG_TX_DRVCTRL_TX2LN0_PORT2, \
>> >-				      _ICL_MG_TX_DRVCTRL_TX2LN1_PORT1)
>> >+#define MG_TX_DRVCTRL_TX1LN0_PORT1			0x168144
>> >+#define MG_TX_DRVCTRL_TX1LN1_PORT1			0x168544
>> >+#define MG_TX_DRVCTRL_TX1LN0_PORT2			0x169144
>> >+#define MG_TX_DRVCTRL_TX1LN1_PORT2			0x169544
>> >+#define MG_TX_DRVCTRL_TX1LN0_PORT3			0x16A144
>> >+#define MG_TX_DRVCTRL_TX1LN1_PORT3			0x16A544
>> >+#define MG_TX_DRVCTRL_TX1LN0_PORT4			0x16B144
>> >+#define MG_TX_DRVCTRL_TX1LN1_PORT4			0x16B544
>> >+#define MG_TX1_DRVCTRL(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_PORT1, \
>> >+				 MG_TX_DRVCTRL_TX1LN0_PORT2, \
>> >+				 MG_TX_DRVCTRL_TX1LN1_PORT1)
>> >+
>> >+#define MG_TX_DRVCTRL_TX2LN0_PORT1			0x1680C4
>> >+#define MG_TX_DRVCTRL_TX2LN1_PORT1			0x1684C4
>> >+#define MG_TX_DRVCTRL_TX2LN0_PORT2			0x1690C4
>> >+#define MG_TX_DRVCTRL_TX2LN1_PORT2			0x1694C4
>> >+#define MG_TX_DRVCTRL_TX2LN0_PORT3			0x16A0C4
>> >+#define MG_TX_DRVCTRL_TX2LN1_PORT3			0x16A4C4
>> >+#define MG_TX_DRVCTRL_TX2LN0_PORT4			0x16B0C4
>> >+#define MG_TX_DRVCTRL_TX2LN1_PORT4			0x16B4C4
>> >+#define MG_TX2_DRVCTRL(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \
>> >+				 MG_TX_DRVCTRL_TX2LN0_PORT2, \
>> >+				 MG_TX_DRVCTRL_TX2LN1_PORT1)

All the _DRVCTRL_* registers, by naming convention are better off to be named _TXxLNx_TXPORTx instead of TXxLNx_PORTx

Anusha 
>> > #define CRI_TXDEEMPH_OVERRIDE_11_6(x)			((x) << 24)
>> > #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK			(0x3F
>> ><< 24)
>> > #define CRI_TXDEEMPH_OVERRIDE_EN			(1 << 22)
>> > #define CRI_TXDEEMPH_OVERRIDE_5_0(x)			((x) << 16)
>> > #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK			(0x3F
><< 16)
>> >+#define CRI_LOADGEN_SEL(x)				((x) << 12)
>> >+#define CRI_LOADGEN_SEL_MASK				(0x3 << 12)
>> >+
>> >+#define MG_CLKHUB_LN0_PORT1			0x16839C
>> >+#define MG_CLKHUB_LN1_PORT1			0x16879C
>> >+#define MG_CLKHUB_LN0_PORT2			0x16939C
>> >+#define MG_CLKHUB_LN1_PORT2			0x16979C
>> >+#define MG_CLKHUB_LN0_PORT3			0x16A39C
>> >+#define MG_CLKHUB_LN1_PORT3			0x16A79C
>> >+#define MG_CLKHUB_LN0_PORT4			0x16B39C
>> >+#define MG_CLKHUB_LN1_PORT4			0x16B79C
>> >+#define MG_CLKHUB(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \
>> >+				 MG_CLKHUB_LN0_PORT2, \
>> >+				 MG_CLKHUB_LN1_PORT1)
>> >+#define CFG_LOW_RATE_LKREN_EN				(1 << 11)
>> >+
>> >+#define MG_TX_DCC_TX1LN0_PORT1			0x168110
>> >+#define MG_TX_DCC_TX1LN1_PORT1			0x168510
>> >+#define MG_TX_DCC_TX1LNO_PORT2			0x169110
>> >+#define MG_TX_DCC_TX1LN1_PORT2			0x169510
>> >+#define MG_TX_DCC_TX1LNO_PORT3			0x16A110
>> >+#define MG_TX_DCC_TX1LN1_PORT3			0x16A510
>> >+#define MG_TX_DCC_TX1LNO_PORT4			0x16B110
>> >+#define MG_TX_DCC_TX1LN1_PORT4			0x16B510
>> >+#define MG_TX1_DCC(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \
>> >+				 MG_TX_DCC_TX1LNO_PORT2, \
>> >+				 MG_TX_DCC_TX1LN1_PORT1)
>> >+#define MG_TX_DCC_TX2LN0_PORT1			0x168090
>> >+#define MG_TX_DCC_TX2LN1_PORT1			0x168490
>> >+#define MG_TX_DCC_TX2LNO_PORT2			0x169090
>> >+#define MG_TX_DCC_TX2LN1_PORT2			0x169490
>> >+#define MG_TX_DCC_TX2LNO_PORT3			0x16A090
>> >+#define MG_TX_DCC_TX2LN1_PORT3			0x16A490
>> >+#define MG_TX_DCC_TX2LNO_PORT4			0x16B090
>> >+#define MG_TX_DCC_TX2LN1_PORT4			0x16B490
>> >+#define MG_TX2_DCC(port, ln) \
>> >+	MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \
>> >+				 MG_TX_DCC_TX2LNO_PORT2, \
>> >+				 MG_TX_DCC_TX2LN1_PORT1)
>> >
>> > /* The spec defines this only for BXT PHY0, but lets assume that
>> >this
>> >  * would exist for PHY1 too if it had a second channel.
>> >--
>> >2.7.4
>> >
>> >_______________________________________________
>> >Intel-gfx mailing list
>> >Intel-gfx at lists.freedesktop.org
>> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx


More information about the Intel-gfx mailing list