[Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-06-06 13:48:45)
> @@ -204,6 +211,12 @@ engines_sample(struct drm_i915_private *dev_priv, unsigned int period_ns)
>                 if (val & RING_WAIT_SEMAPHORE)
>                         add_sample(&engine->pmu.sample[I915_SAMPLE_SEMA],
>                                    period_ns);
> +
> +               if (engine->pmu.enable & BIT(I915_SAMPLE_QUEUED))
> +                       add_sample_mult(&engine->pmu.sample[I915_SAMPLE_QUEUED],
> +                                       atomic_read(&engine->request_stats.queued),
> +                                       (u64)period_ns *
> +                                       I915_SAMPLE_QUEUED_DIVISOR / 1000000);

Doesn't this promote to a 64b divide?
-Chris