[Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers

[Srivatsa, Anusha]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf Of
>Paulo Zanoni
>Sent: Monday, May 21, 2018 5:26 PM
>To: intel-gfx at lists.freedesktop.org
>Cc: Zanoni, Paulo R <paulo.r.zanoni at intel.com>
>Subject: [Intel-gfx] [PATCH 15/24] drm/i915/icl: compute the TBT PLL registers
>
>Use the hardcoded tables provided by our spec.
>
>Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>index 72f15e727d07..8a34733de1ea 100644
>--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
>@@ -2452,6 +2452,16 @@ static const struct skl_wrpll_params
>icl_dp_combo_pll_19_2MHz_values[] = {
> 	  .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},  };
>
>+static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
>+	.dco_integer = 0x151, .dco_fraction = 0x4000,
>+	.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
>+static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
>+	.dco_integer = 0x1A5, .dco_fraction = 0x7000,
>+	.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, };
>+
> static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,
> 				  struct skl_wrpll_params *pll_params)  { @@ -
>2494,6 +2504,14 @@ static bool icl_calc_dp_combo_pll(struct drm_i915_private
>*dev_priv, int clock,
> 	return true;
> }
>
>+static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,
>+			     struct skl_wrpll_params *pll_params) {
>+	*pll_params = dev_priv->cdclk.hw.ref == 24000 ?
>+			icl_tbt_pll_24MHz_values : icl_tbt_pll_19_2MHz_values;
>+	return true;
>+}
>+
> static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> 				struct intel_encoder *encoder, int clock,
> 				struct intel_dpll_hw_state *pll_state) @@ -
>2501,9 +2519,12 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	uint32_t cfgcr0, cfgcr1;
> 	struct skl_wrpll_params pll_params = { 0 };
>+	bool is_tbt = encoder->port >= PORT_C;
> 	bool ret;
>
>-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>+	if (is_tbt)
>+		ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
>+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> 		ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
> 	else
> 		ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); @@ -
>2513,6 +2534,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state
>*crtc_state,
>
> 	cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
> 		 pll_params.dco_integer;
>+	if (is_tbt)
>+		cfgcr0 |= DPLL_CFGCR0_SSC_ENABLE_ICL;
Paulo,
TBT has some TBT specific CFGCR0 registers which needs to be configured here. 

Anusha 
> 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
> 		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
>--
>2.14.3
>
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