[Intel-gfx] [PATCH 05/17] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories

[Joonas Lahtinen]

Quoting Chris Wilson (2018-06-10 22:43:13)
> When we update the gen6 ppgtt page directories, we do so by writing the
> new address into a reserved slot in the GGTT. It appears that when the
> GPU reads that entry from the gsm, it uses its small cache and that we
> need to invalidate that cache after writing. We don't see an issue
> currently as we prefill the ppgtt page directories on creation; and only
> create the single aliasing_ppgtt long before we start using the GGTT
> (and so before the cache mayhave a conflicting entry).

"may have"

> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Matthew Auld <matthew.william.auld at gmail.com>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>

Regards, Joonas