[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER

Patchwork patchwork at emeril.freedesktop.org
Fri Jun 15 11:06:44 UTC 2018 

== Series Details ==

Series: ICELAKE DSI DRIVER
URL   : https://patchwork.freedesktop.org/series/44823/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
c891c2690e61 drm/i915/icl: Define register for DSI PLL
034415bf480c drm/i915/icl: Program DSI Escape clock Divider
-:38: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

-:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#89: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:47:
+		I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

-:95: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#95: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:53:
+		I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
+				esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);

-:100: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#100: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:58:
+static void __attribute__((unused)) gen11_dsi_pre_enable(

total: 0 errors, 1 warnings, 3 checks, 79 lines checked
377567cee3fb drm/i915/icl: Define DSI mode ctl register
0c9ae5501a9c drm/i915/icl: Enable DSI IO power
cb9ea5efade8 drm/i915/icl: Define PORT_CL_DW_10 register
159663d4b051 drm/i915/icl: Power down unused DSI lanes
ead6060f69a5 drm/i915/icl: Define AUX lane registers for Port A/B
873188f7da58 drm/i915/icl: Configure lane sequencing of combo phy transmitter
60ff8f5c139f drm/i915/icl: DSI vswing programming sequence
-:31: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#31: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:40:
+	for_each_dsi_port(port, intel_dsi->ports) {
+

total: 0 errors, 0 warnings, 1 checks, 132 lines checked
cb25fce515b5 drm/i915/icl: Enable DDI Buffer
1c8e8d05b24e drm/i915/icl: Define T_INIT_MASTER registers
03cfa39b2778 drm/i915/icl: Program T_INIT_MASTER registers
d55b00eb762f drm/i915/icl: Define data/clock lanes dphy timing registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:9905:
+#define  CLK_PREP_TIME(x)		(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:9907:
+#define  CLK_ZERO_TIME(x)		(x << 20)

-:35: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:9909:
+#define  CLK_PRE_TIME(x)		(x << 16)

-:37: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:9911:
+#define  CLK_POST_TIME(x)		(x << 8)

-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:9913:
+#define  CLK_TRAIL_TIME(x)		(x << 0)

-:52: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#52: FILE: drivers/gpu/drm/i915/i915_reg.h:9926:
+#define  HS_PREP_TIME(x)		(x << 24)

-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/i915/i915_reg.h:9928:
+#define  HS_ZERO_TIME(x)		(x << 16)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:9930:
+#define  HS_TRAIL_TIME(x)		(x << 8)

-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/i915_reg.h:9932:
+#define  HS_EXIT_TIME(x)		(x << 0)

total: 0 errors, 0 warnings, 9 checks, 46 lines checked
0f1272e068f1 drm/i915/icl: Program DSI clock and data lane timing params
-:80: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#80: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:631:
+	ths_prepare_ns = max(mipi_config->ths_prepare,
+				mipi_config->tclk_prepare);

-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:655:
+		clk_zero_cnt = DIV_ROUND_UP(

-:128: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#128: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:669:
+		hs_zero_cnt = DIV_ROUND_UP(

-:190: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#190: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:727:
+		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
+							ui_num * mul);

-:196: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#196: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:731:
+			DRM_DEBUG_KMS("prepare count too high %u\n",
+								prepare_cnt);

-:201: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#201: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:736:
+		exit_zero_cnt = DIV_ROUND_UP(

-:226: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#226: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:748:
+		if (exit_zero_cnt < (55 * ui_den / ui_num) &&
+					(55 * ui_den) % ui_num)

-:231: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#231: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:753:
+			DRM_DEBUG_KMS("exit zero count too high %u\n",
+								exit_zero_cnt);

-:250: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#250: FILE: drivers/gpu/drm/i915/intel_dsi_vbt.c:764:
+			DRM_DEBUG_KMS("clock zero count too high %u\n",
+								clk_zero_cnt);

total: 0 errors, 0 warnings, 9 checks, 293 lines checked
baa4e013e1cc drm/i915/icl: Define TA_TIMING_PARAM registers
-:31: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#31: FILE: drivers/gpu/drm/i915/i915_reg.h:9945:
+#define  TA_SURE_TIME(x)		(x << 16)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked
f0613ae3d0c5 drm/i915/icl: Program TA_TIMING_PARAM registers
dc59f86128ed drm/i915/icl: Get DSI transcoder for a given port
-:37: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#37: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:31:
+static enum transcoder __attribute__((unused)) dsi_port_to_transcoder(

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
8ec34fab7e4a drm/i915/icl: Add macros for MMIO of DSI transcoder registers
a6e5e2fd35e0 drm/i915/icl: Define TRANS_DSI_FUNC_CONF register
-:26: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:9959:
+#define  OP_MODE(x)			(x << 28)

-:33: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#33: FILE: drivers/gpu/drm/i915/i915_reg.h:9966:
+#define  PIX_FMT(x)			(x << 16)

-:43: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#43: FILE: drivers/gpu/drm/i915/i915_reg.h:9976:
+#define  PIX_VIRT_CHAN(x)		(x << 12)

-:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:9978:
+#define  PIX_BUF_THRESHOLD(x)		((x & 0x3) << 10)

-:51: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#51: FILE: drivers/gpu/drm/i915/i915_reg.h:9984:
+#define  CONTINUOUS_CLK(x)		(x << 8)

-:56: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:9989:
+#define  LINK_CALIBRATION(x)		(x << 4)

-:61: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:9994:
+#define  S3D_ORIENTATION(x)		(x << 1)

total: 0 errors, 0 warnings, 7 checks, 53 lines checked
93beeefce6e7 drm/i915/icl: Configure DSI transcoders
-:66: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#66: FILE: drivers/gpu/drm/i915/intel_dsi_new.c:360:
+			tmp |= LINK_CALIBRATION(

total: 0 errors, 0 warnings, 1 checks, 121 lines checked

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